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b84b709182
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61 Commits

Author SHA1 Message Date
Ross Thompson
b84b709182 Optimized way selection logic. 2022-12-04 12:30:56 -06:00
Ross Thompson
74d5ccc2b1 Found possible optimization as the way selection is shared in cache, cacheway, and cachelru. 2022-12-04 01:20:51 -06:00
Ross Thompson
62e495c739 Moved selectedway mux into cacheway. It makes way more sense there. 2022-12-04 01:15:47 -06:00
Ross Thompson
cb310bfb1d Removed unused port on cacheway. 2022-12-01 11:47:48 -06:00
Ross Thompson
813b2963fb More optimization. 2022-11-30 11:26:48 -06:00
Ross Thompson
da7b13ba0a Removed reset on dirty cache bits. 2022-11-30 11:04:37 -06:00
Ross Thompson
5e5cca6ae1 Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now. 2022-11-30 11:01:25 -06:00
Ross Thompson
ac3e02692b Preparing to merge dirty and tag srams. 2022-11-30 10:40:48 -06:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
e3577781b0 Optimization of cacheway. 2022-11-29 18:30:47 -06:00
Ross Thompson
9e4166407b Fixed a bug with the replacement policy. It was updating the wrong set on load hits. 2022-11-29 14:51:09 -06:00
Ross Thompson
179d321683 Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled. 2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378 Renamed signals in the cache. 2022-11-29 10:52:40 -06:00
Ross Thompson
f03d5d3ac8 Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
1a00e7bbee Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
42c0a10d07 Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
8a6ca027c2 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
f7e64fcd69 Fixed fstore2 in cache? 2022-08-01 22:04:44 -05:00
Ross Thompson
0f586c9ed3 Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Ross Thompson
ffda64587c Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added. 2022-07-18 23:37:18 -05:00
Ross Thompson
a88543275f Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN. 2022-07-17 21:05:31 -05:00
Ross Thompson
3670c47141 Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width. 2022-07-17 16:20:04 -05:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Ross Thompson
6d914def08 Name cleanup. 2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9 Signal name cleanup. 2022-03-10 18:26:58 -06:00
Ross Thompson
67ef46ea92 Partially working byte write enables. Works for cache, but not dtim or bus only. 2022-03-10 16:11:39 -06:00
Ross Thompson
7a129c75cd Added byte write enables to cache SRAMs. 2022-03-10 15:48:31 -06:00
Ross Thompson
e852cb8a31 Eliminated more ports in cacheway. 2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d More cache cleanup. 2022-02-13 15:47:27 -06:00
Ross Thompson
a5ad4331ec More cache cleanup. 2022-02-13 12:38:39 -06:00
Ross Thompson
dd944265aa Formating improvements to cache. 2022-02-11 23:10:58 -06:00
Ross Thompson
f716cce832 Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
88c7a94aa9 Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
7810a09782 Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
4a7ebb3757 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
e2191e3637 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
Ross Thompson
da2dca9816 Removed VDWriteEnable. 2022-02-07 21:59:18 -06:00
Ross Thompson
359a23237d Progress towards simplifying the cache's write enables. 2022-02-07 17:23:09 -06:00
Ross Thompson
459054900f Optimization of cache save/restore. 2022-02-04 14:21:04 -06:00
Ross Thompson
7c1f7e335c Working first cut of the cache changes moving the replay to a save/restore. 
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
 2022-02-04 13:31:32 -06:00
David Harris
97d31cec21 sram1rw cleanup 2022-02-03 17:50:23 +00:00