Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
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This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
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only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
40af3abef9
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
c97572d209
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
c9c3bddc6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
cb68548b88
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
b3ebce0365
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
1c96b22b8f
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
2b8e8707a7
Floating point test cleanup
2022-01-06 21:45:16 +00:00
David Harris
2b4c81fe98
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
55e757db03
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
d30ad136f3
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b
Changed names of address in caches.
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Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
3517db6b64
Fixed xilinx synth error with $error in extend.sv
2022-01-05 17:48:08 -06:00
Ross Thompson
fb3207fc72
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 16:57:29 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
David Harris
30c1ab5213
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-05 22:10:33 +00:00
David Harris
355efda9bc
Replaced exe2memfile with SiFive elf2hex
2022-01-05 22:10:26 +00:00
Ross Thompson
bd901cd125
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-05 14:15:27 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
David Harris
85fa620cfb
Finished removing generate statements
2022-01-05 16:41:17 +00:00
David Harris
32590d484c
Removed more generate statements
2022-01-05 16:25:08 +00:00
David Harris
f04856ee94
Removed more generate statements
2022-01-05 16:01:03 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd
the i and d caches now share common verilog.
2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd
parameterized the caches with the goal of using common rtl for both i and d caches.
2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4
Switched block for line in caches.
2022-01-04 22:08:18 -06:00
Ross Thompson
d94a1c6404
Fixed bug where last line of dcache was not written back to memory on dcache flush.
2022-01-04 21:55:48 -06:00
Ross Thompson
3c3c6d0fe8
Fixed dcache flush.
2022-01-04 18:40:58 -06:00
David Harris
1f07470477
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-04 19:47:51 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
