61 Commits

Author	SHA1	Message	Date
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	b16846bddb	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Ross Thompson	00de91cc87	Added FlushF to hazard unit. ... Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.	2021-02-19 16:36:51 -06:00
Ross Thompson	5df7e959f3	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00