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Author SHA1 Message Date
Kip Macsai-Goren
3e19eba20d updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop 2021-06-22 11:21:11 -04:00
bbracker
9b27cd6fb7 added slack notifier for long sims 2021-06-22 08:31:41 -04:00
Ross Thompson
f79e5eaa47 Icache now uses physical lenght bits rather than XLEN. 2021-06-21 16:41:09 -05:00
Ross Thompson
3cbe4c9bc2 Improved some names in icache. 2021-06-21 16:40:37 -05:00
Kip Macsai-Goren
c0d52b905d updated mmu test pagetables so that make can be run. 2021-06-21 12:26:47 -04:00
David Harris
7930c2ebb4 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
David Harris
5d6dc82db2 Added Physical Address and Size to PMA Checker/MMU 2021-06-21 01:27:02 -04:00
David Harris
1ec90a5e1f Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
David Harris
d2ec04564b Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
bbracker
bf3c2dc089 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 22:29:40 -04:00
bbracker
3000c27acd linux actually uses FPU now! 2021-06-20 22:29:21 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
2643130c41 read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
14ae87ff0a testbench update b/c QEMU extends 32b CSRs to 64b 2021-06-20 09:24:19 -04:00
bbracker
83a0a37f8e make xCOUNTEREN what buildroot expects it to be 2021-06-20 09:22:31 -04:00
bbracker
dc26f2a6d0 whoops wavedo typo 2021-06-20 05:36:54 -04:00
bbracker
c77aabdc6f make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
918ff5093a MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
069a79fafd workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
086f031b84 remove lingering busybear stuff from buildroot do files 2021-06-20 00:50:53 -04:00
bbracker
8462f248aa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 00:40:44 -04:00
bbracker
d62d9a7aac make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
Ross Thompson
70c45a5349 Revert "Icache now uses physical lenght bits rather than XLEN." 
This reverts commit 16266d978a.
 2021-06-19 08:58:34 -05:00
Ross Thompson
868ddce5f2 Revert "Improved some names in icache." 
This reverts commit a57c63aa7b.
 2021-06-19 08:58:32 -05:00
bbracker
a3eafc6e5b change buildroot config to use relative path for testvectors 2021-06-18 22:28:07 -04:00
bracker
26512348b0 gitignore merge 2021-06-18 21:12:05 -05:00
bracker
34f17b90ea handle tera usernames more gracefully 2021-06-18 21:11:14 -05:00
bbracker
1781ae9c93 on-Tera solution for sym linking to linux testvectors 2021-06-18 22:01:18 -04:00
bracker
cd7d403f92 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 20:41:01 -05:00
bracker
0addf4a297 script support for copying large files from tera 2021-06-18 20:40:19 -05:00
Kip Macsai-Goren
7a0b74d8bb fixed trap handler, maker errors, pagetables still need work. 2021-06-18 18:13:08 -04:00
Kip Macsai-Goren
a74ec082a1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 18:08:07 -04:00
bbracker
cb949851d9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 17:37:49 -04:00
bbracker
8d242d73b5 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
Kip Macsai-Goren
5c388caef6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 13:27:10 -04:00
Ross Thompson
99e3a0db28 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-06-18 12:24:42 -05:00
Ross Thompson
a57c63aa7b Improved some names in icache. 2021-06-18 12:22:41 -05:00
Ross Thompson
16266d978a Icache now uses physical lenght bits rather than XLEN. 2021-06-18 12:02:59 -05:00
David Harris
33312caeb1 Restored wally-busybear testbench now that graphical sim is working 2021-06-18 12:36:25 -04:00
bbracker
03a45aeef1 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
Abe
a0a4b09c94 Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
Kip Macsai-Goren
e463247364 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 10:46:43 -04:00
bbracker
5095c73dde Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 09:49:37 -04:00
bbracker
4f50dd575d buildroot added to regression because it passes regression 2021-06-18 09:49:30 -04:00
David Harris
580ac1c4df Made MemPAdrM and related signals PA_BITS wide 2021-06-18 09:36:22 -04:00
David Harris
de221ff2d0 Changed physical addresses to PA_BITS in size in MMU and TLB 2021-06-18 09:11:31 -04:00
bbracker
c25905ac70 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-18 08:15:40 -04:00
bbracker
faae30c31c remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
df7e373c69 Cleaned up PMAAccessFult logic but it still doesn't accomdate TIM and BootTim depending on AccessRWX 2021-06-18 08:13:15 -04:00