DTowersM
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8903af3764
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-05-31 20:13:41 +00:00 |
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DTowersM
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0de54a01bf
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removed delapidated signals SIE_REGW SIP_REGW TimerIntM SwIntM
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2022-05-31 20:10:56 +00:00 |
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Katherine Parry
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4ed7933aa3
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added unpackinput.sv
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2022-05-31 16:18:50 +00:00 |
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slmnemo
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4a8d0be32c
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Reverted commit 60e3d7d81b
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2022-05-28 04:00:01 -07:00 |
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slmnemo
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f18989e801
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Revert Commit 6c61840045
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2022-05-28 03:35:17 -07:00 |
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slmnemo
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60e3d7d81b
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Changed NO_IE_MTIME_CHECKPOINT so it uses the new parameter name
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2022-05-28 03:16:55 -07:00 |
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slmnemo
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6c61840045
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Deparametrized Linux testbench and removed mentions of parameters in wally-pipelined.do
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2022-05-28 03:14:49 -07:00 |
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Katherine Parry
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1be91753fe
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moved lzc to generic and small optimizations on fcvt
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2022-05-27 09:04:02 -07:00 |
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slmnemo
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a2300f063d
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added a todo to riscv-wally so that long buildroot looks for a successful boot rather than a specific instruction
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2022-05-25 17:40:57 -07:00 |
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Katherine Parry
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f35450207f
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single and double conversions pass all tests
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2022-05-25 23:02:02 +00:00 |
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slmnemo
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0398aa02a0
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fixed a comment spelling typo
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2022-05-23 19:24:28 -07:00 |
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Katherine Parry
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5d34db85b2
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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slmnemo
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11e703c8c0
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fixed lint autofailing due to no log being produced in regression-wally
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2022-05-19 18:30:59 -07:00 |
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slmnemo
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79c28d34dc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-05-19 17:51:45 -07:00 |
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slmnemo
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e4024eb503
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Added parameters for DEBUG_TRACE to buildroot, buildroot-checkpoint, and buildroot-notrace
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2022-05-19 17:51:26 -07:00 |
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slmnemo
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e33ca59d46
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Added parameter to keep tracking on for buildroot and buildroot-checkpoint in regression.py
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2022-05-19 17:50:48 -07:00 |
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slmnemo
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89c7438424
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parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do
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2022-05-19 16:21:38 -07:00 |
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Katherine Parry
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6f2d8c24ad
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Bug fixed in unpacker and sub/add/mul tests pass TestFloat
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2022-05-19 20:31:23 +00:00 |
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Katherine Parry
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738bbf6479
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Added fp tests - doesnpass yet
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2022-05-19 16:32:30 +00:00 |
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slmnemo
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c96f07ad75
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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slmnemo
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23d6791b22
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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slmnemo
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1ff47888a7
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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Kip Macsai-Goren
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b155effe66
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put privileged tests back into rv32/64gc
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2022-05-04 21:20:25 +00:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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David Harris
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bcd8728b3e
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Switched to behavioral comparator for best PPA
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2022-05-03 11:00:39 +00:00 |
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Kip Macsai-Goren
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4b00531d77
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fixed incorrect configs in regression
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2022-04-25 19:28:47 +00:00 |
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Kip Macsai-Goren
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74b103fae4
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added working tests to test list, updated regression for new configs
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2022-04-25 19:18:15 +00:00 |
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David Harris
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04b0579b89
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Extended sim time to fully boot Linux. Added comments to hazard unit
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2022-04-24 13:51:00 +00:00 |
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Ross Thompson
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a86274a1e0
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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6504017044
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Run 4M instructions in buildroot test to get through kernel & VirtMem startup
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2022-04-18 01:29:38 +00:00 |
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David Harris
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6769f0cb43
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Added comments in fcvt
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2022-04-17 16:53:10 +00:00 |
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Ross Thompson
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55c667b60d
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Commented output power analysis to speed simulation.
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2022-04-16 15:32:59 -05:00 |
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Ross Thompson
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56bea58a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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23406d0926
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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David Harris
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23da303ad3
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Added bootmem source ccode
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2022-04-05 23:22:53 +00:00 |
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Ross Thompson
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400b5f7632
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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Ross Thompson
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3ebb7f1057
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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Kip Macsai-Goren
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37c755e6ce
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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691f1a6b0d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 17:18:25 -05:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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bbracker
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9d26bfe71d
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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Kip Macsai-Goren
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eb337fd3e1
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added test config that doesn't use compressed instructions for privileged tests
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2022-03-28 19:12:31 +00:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Skylar Litz
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62a330c290
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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bbracker
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d645666fe7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:06:27 +00:00 |
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bbracker
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79ff8d3c80
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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David Harris
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6431ad4a8b
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
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2022-03-03 15:38:08 +00:00 |
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bbracker
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87aad1d953
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fix peripheral test and add it to regression
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2022-03-02 23:44:39 +00:00 |
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bbracker
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e9e827c83e
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add CSRs to waveview
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2022-03-02 18:31:10 +00:00 |
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