Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,409 Commits 14 Branches 1 Tag 31 MiB
8d65d50085
Commit Graph

393 Commits

Author SHA1 Message Date
bbracker
82fc766819 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
5e18a15a4c Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Ross Thompson
3951eb56f5 Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
Ross Thompson
49f6eec579 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1 Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
d3dd70e3e6 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
20cd0e208b added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ben Bracker
59b177beac stop busybear from hanging 2021-07-02 17:22:09 -05:00
bbracker
13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
Katherine Parry
7e3483b283 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
bbracker
13df69abdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-24 01:42:41 -04:00
bbracker
be962cb1ff overhauled linux testbench and spoofed MTTIME interrupt 2021-06-24 01:42:35 -04:00
Katherine Parry
8eed89616c fpu clean-up 2021-06-23 16:42:40 -04:00
Katherine Parry
353a27f12f rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
David Harris
7930c2ebb4 Commented out 100k tests to improve speed 2021-06-21 01:43:18 -04:00
David Harris
1ec90a5e1f Reversed [0:...] with [...:0] in bus widths across the project 2021-06-21 01:17:08 -04:00
bbracker
bf3c2dc089 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-06-20 22:29:40 -04:00
bbracker
3000c27acd linux actually uses FPU now! 2021-06-20 22:29:21 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
2643130c41 read from MSTATUS workaround because QEMU has incorrect MSTATUS 2021-06-20 10:11:39 -04:00
bbracker
14ae87ff0a testbench update b/c QEMU extends 32b CSRs to 64b 2021-06-20 09:24:19 -04:00
bbracker
c77aabdc6f make buildroot ignore SSTATUS because QEMU did not originally log it 2021-06-20 05:31:24 -04:00
bbracker
918ff5093a MSTATUS workaround 2021-06-20 04:48:09 -04:00
bbracker
069a79fafd workaround for ignoring MTIME 2021-06-20 02:26:39 -04:00
bbracker
d62d9a7aac make buildroot waves only turn on after a user-specified point 2021-06-20 00:39:30 -04:00
bbracker
8d242d73b5 fixed PCtext error by using blocking assignments 2021-06-18 17:37:40 -04:00
bbracker
03a45aeef1 restore graphical buildroot sim 2021-06-18 11:58:16 -04:00
bbracker
faae30c31c remove unused testbench-busybear.sv 2021-06-18 08:15:19 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00