220 Commits

Author	SHA1	Message	Date
David Harris	8cbdbb1c38	lsu simplification	2022-08-25 18:52:42 -07:00
David Harris	d507bb3d70	busfsm simplified	2022-08-25 18:36:53 -07:00
David Harris	dc52f55aa6	Removed unused signals	2022-08-25 18:34:39 -07:00
David Harris	50826c0b61	Removed unused signals	2022-08-25 18:30:46 -07:00
David Harris	7cbca2dd22	Removed UncachedBusRead and UncachedBusWrite	2022-08-25 18:24:39 -07:00
David Harris	845807a329	Restored ahbtranstype	2022-08-25 18:22:26 -07:00
David Harris	4ab678ed48	Removed ahbtranstype	2022-08-25 18:21:45 -07:00
David Harris	f405a191af	Removed WordCountFlag	2022-08-25 18:21:18 -07:00
David Harris	db7698202d	Removed UncachedAccess	2022-08-25 18:20:52 -07:00
David Harris	7801ed48b3	Removed UncachedRW	2022-08-25 18:19:41 -07:00
David Harris	bb4ae908db	Removed CacheBusAck	2022-08-25 18:17:34 -07:00
David Harris	85b5587678	Removed SelUncachedAdr	2022-08-25 18:15:59 -07:00
David Harris	555083b0c3	Removed Cache_Enabled	2022-08-25 18:13:34 -07:00
David Harris	b982db5bd5	Removed STATE_BUS_FETCH and STATE_BUS_WRITE	2022-08-25 18:12:09 -07:00
David Harris	de9ec7cc2e	Removed CacheFetchLine and CacheWriteLine	2022-08-25 18:10:15 -07:00
David Harris	fb5ddc476c	Removed CountEn	2022-08-25 18:05:44 -07:00
David Harris	7eae6765df	Removed wordcount	2022-08-25 18:04:49 -07:00
David Harris	73419f0d41	Added buscachefsm for system with bus and cache	2022-08-25 18:01:01 -07:00
David Harris	0b918d6916	Separated busdp for cache from simpler logic for no cache	2022-08-25 17:54:04 -07:00
David Harris	5c1934208a	Simplified swbytemask	2022-08-25 17:32:16 -07:00
David Harris	352bf88ac0	FIxed wallypipelinedsoc merge conflict	2022-08-25 15:36:47 -07:00
David Harris	b96942e84c	Removed delayed AHB signals from top level	2022-08-25 15:34:14 -07:00
Ross Thompson	ad3e632119	Almost fixed issues with irom and dtim address selection.	2022-08-25 15:52:25 -05:00
Ross Thompson	bbf668e460	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 14:45:02 -05:00
David Harris	5b3c68fe74	ahblite cleanup	2022-08-25 12:44:25 -07:00
Ross Thompson	502eb0f5d1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-25 14:40:52 -05:00
David Harris	d7be94fab2	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	7a129af9ad	Removed M sufix from busdp signals	2022-08-25 11:13:01 -07:00
David Harris	84ba62a04c	Renamed LSUFunct3M to Funct3 in busdp	2022-08-25 11:08:12 -07:00
David Harris	78618f5fc0	Renaming LSU signals from busdp	2022-08-25 11:05:10 -07:00
David Harris	cd02c894df	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
David Harris	5dc4fb757a	Continued busdp/ebu simplification	2022-08-25 10:20:02 -07:00
David Harris	89860588b8	Renamed AHB signals coming out of LSU to LSH_<AHBNAME>	2022-08-25 09:52:08 -07:00
Ross Thompson	bd9401179d	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
David Harris	4ecdbb308a	Renamed DCache to Cache in busdp/busfsm signal interface	2022-08-25 06:21:22 -07:00
David Harris	cb2c0fe027	Minor name cleanups	2022-08-25 04:28:25 -07:00
David Harris	a3828420c0	Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM	2022-08-25 04:06:27 -07:00
David Harris	fe3147806d	removed simpleram and modified dtim to use bram1p1rw	2022-08-25 03:39:57 -07:00
Ross Thompson	b650d7e05a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	c6927d2ace	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Ross Thompson	0c52c7f69c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-23 18:52:15 -05:00
Ross Thompson	ee3d968da0	Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.	2022-08-23 18:51:11 -05:00
David Harris	27cca2e3fd	Fixed LSU typos	2022-08-23 10:23:08 -07:00
Ross Thompson	b9fadc11c3	Replaced LSU data replication with 0 extention.	2022-08-23 10:43:47 -05:00
Ross Thompson	cd0da2e3b3	Updated the names of the *WriteDataM inside the LSU to more meaningful names. ... Moved the FWriteDataMux so that the bus and dtim both get fpu stores. Modified the PMA to disallow double sized reads when XLEN=32.	2022-08-23 10:34:39 -05:00
David Harris	7c91ed38a3	LSU minor edits	2022-08-23 07:35:47 -07:00
David Harris	a9a5285ba8	Named HTRANS states in busfsm	2022-08-22 13:56:46 -07:00
David Harris	34eece10b8	Finished FPU-LSU interface cleanup	2022-08-22 13:43:04 -07:00
David Harris	bf54c1c868	Simplified FPU-LSU interface to skip IEU	2022-08-22 13:29:20 -07:00
Ross Thompson	21526957cf	Updated fpga test bench. ... Solved read delay cache bug. Introduced during cache optimizations.	2022-08-21 15:59:54 -05:00