David Harris
8b23162d6d
Fixed adrdecs to use Access signals for TIMs
2021-07-05 23:42:58 -04:00
David Harris
71711c54c9
Don't generate HPTW when MEM_VIRTMEM=0
2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7
Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b
Fixed combo loop in the page table walker.
2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-05 16:07:27 -05:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
07f2064c19
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
Ross Thompson
b2c5c3f637
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 17:07:57 -05:00
David Harris
b0f199b574
Fixed TLB_ENTRIES merge conflict and handling of global PTEs
2021-07-04 18:05:22 -04:00
Ross Thompson
02721c29dc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:54:31 -05:00
David Harris
8b707f7703
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:53:08 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
Ross Thompson
a252416535
Removed the TranslationVAdrQ as it is not necessary.
2021-07-04 16:49:34 -05:00
Ross Thompson
7f62808544
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
David Harris
07ef67e537
Restructured TLB Read as AND-OR operation with one-hot match/read line
2021-07-04 17:01:22 -04:00
David Harris
8337d6df68
Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders
2021-07-04 16:33:13 -04:00
David Harris
c281539f36
TLB cleanup
2021-07-04 14:59:04 -04:00
David Harris
81742ef9e2
TLB cleanup
2021-07-04 14:37:53 -04:00
David Harris
152923e552
TLB minor organization
2021-07-04 14:30:56 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
1b39481a16
TLB mux and swizzling cleanup
2021-07-04 12:53:52 -04:00
David Harris
735f3b4217
Replaced generates with arrays in TLB
2021-07-04 12:32:27 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
ccd9c05303
Switched to array notation for pmpchecker
2021-07-04 10:51:56 -04:00
David Harris
9645b023c9
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 01:19:38 -04:00
Ross Thompson
9f16d08d0d
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
David Harris
1fa4abf7b6
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
David Harris
d44916dacf
Cleaned up PMA/PMP checker unused code
2021-07-03 02:25:31 -04:00
Ross Thompson
cf688bd3f6
Fixed up the physical address generation for 64 bit page table walker.
2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a
Fixed up the bit widths on the page table walker for rv32.
2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
David Harris
c85e0df1ff
Optimized PMP checker logic and added support for configurable number of PMP registers
2021-07-02 11:04:13 -04:00
Ross Thompson
118dfa9cec
added page table walker fault exit for icache.
2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354
Fixed tab space issue.
2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f
Fixed the wrong virtual address write into the dtlb.
2021-07-01 16:55:16 -05:00
Ross Thompson
88a18496cf
Got some stores working in virtual memory.
2021-07-01 12:49:09 -05:00
Ross Thompson
002c32d2ad
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d
Major rewrite of ptw to remove combo loop.
2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742
The icache now correctly interlocks with the PTW on TLB miss.
2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
bc9c944ba0
Don't use this branch walker still broken.
2021-06-28 17:26:11 -05:00
Kip Macsai-Goren
ac597d78c8
Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
2021-06-24 19:59:29 -04:00
Ross Thompson
c02141697d
Fixed combo loop in between the page table walker and i/dtlb.
2021-06-24 13:47:10 -05:00
Kip Macsai-Goren
c8f80967a6
added a few very simple arbitrations in the lsuArb that pass regression. cleaned up a few unused signals. Added several comments and concerns to lsuarb so I can remember where my thoughts were at the end of the day.
2021-06-23 19:59:06 -04:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
a514554eeb
Reduced complexity of pmpadrdec
2021-06-23 03:03:52 -04:00
David Harris
2060a5c2f8
Reduced complexity of pmpadrdec
2021-06-23 02:31:50 -04:00
David Harris
fa51ab9f68
Refactored pmachecker to have adrdecs used in uncore
2021-06-23 01:41:00 -04:00
