James E. Stine
8429078d4f
TV for conversion and compare
2021-10-06 14:38:32 -05:00
James E. Stine
93668b5185
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
James E. Stine
2afa6e7a6e
Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included
2021-10-06 08:56:01 -05:00
Skylar Litz
5bcae393c9
added delayed MIP signal
2021-10-04 18:23:31 -04:00
David Harris
48e33c79a9
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
2ae51d1852
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
fbe6e41169
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
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This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
David Harris
caa36f267d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
bbracker
7117c0493c
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
bbracker
3f96ff0ac0
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
ff5379fd95
fix regression
2021-09-15 17:30:59 -04:00
David Harris
92385a1d51
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-13 12:41:07 -04:00
David Harris
9fa048980d
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
Ross Thompson
cd6d1e0b12
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-13 09:41:34 -05:00
David Harris
7be1160a48
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
Ross Thompson
296da4f437
FPGA test bench and test program.
2021-09-12 20:41:54 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
f8272c45d1
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
da9a366d20
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
b3bc3cf6d0
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
e9a1dc90f6
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
fe378f2692
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
c31b7b4dc5
Wally previously was overcounting retired instructions when they were flushed.
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InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114
Confirmed David's changes to the interrupt code.
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When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
Ross Thompson
6c57002d0e
Added logic to linux test bench to not stop simulation on csr write faults.
2021-08-15 11:13:32 -05:00
Ross Thompson
55fda4de62
Switched ExceptionM to dcache to be just exceptions.
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Added test bench logic to hold forces until the W stage is unstalled.
2021-08-13 15:53:50 -05:00
Ross Thompson
32db21659f
Fixed bugs with CSR checking. The parsing algorithm was messing up the token order after the CSR token.
2021-08-13 14:53:43 -05:00
Ross Thompson
e141a00934
Cleaned up the linux testbench by removing old code and signals.
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Added back in the csr checking logic.
Added code to force timer, external, and software interrupts by using the expected
values from qemu's (m/s)cause registers.
Still need to prevent wally's timer interrupt.
2021-08-13 14:39:05 -05:00
Ross Thompson
9ff9c4dff9
Minor cleanup of the linux test bench.
2021-08-12 11:14:55 -05:00
Ross Thompson
cce0571925
Fixed another bug with the atomic instrucitons implemention in the dcache.
2021-08-08 22:50:31 -05:00
Ross Thompson
fc7016eea6
Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic.
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Fixed logic for trace update in the M and W stages. The M stage should not update if there
is an instruction fault.
2021-08-08 00:28:18 -05:00
Ross Thompson
aa9a5d879b
Finally past the CLINT issues.
2021-08-06 16:41:34 -05:00
Ross Thompson
0bfbcef8ab
Now past the CLINT issues.
2021-08-06 16:16:39 -05:00
Ross Thompson
9be10cdc8b
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
Ross Thompson
c749d08542
fixed the read timer issue but we still have problems with interrupts and i/o devices.
2021-08-06 10:16:06 -05:00
Ross Thompson
3582be4dbb
Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
2021-08-05 16:49:03 -05:00
Ross Thompson
f808b29065
Added some comments to linux testbench.
2021-07-30 17:57:03 -05:00
Ross Thompson
e166cc84ee
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
2021-07-30 14:24:50 -05:00
Ross Thompson
74fba4bb06
Moved the test bench modules to a common directory.
2021-07-30 14:16:14 -05:00
Ross Thompson
d8878581f4
Created new linux test bench and parsing scripts.
2021-07-29 20:26:50 -05:00
Kip Macsai-Goren
3008111bcd
added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
2021-07-23 16:02:42 -04:00
