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976 Commits 14 Branches 1 Tag 31 MiB
802238643a
Commit Graph

64 Commits

Author SHA1 Message Date
David Harris
802238643a Removed two cycles of latency from the DTIM 2021-06-10 10:30:24 -04:00
David Harris
01d6ca1e2a Fixed lint WIDTH errors 2021-06-09 20:58:20 -04:00
David Harris
b613f46c2d Resized BOOT TIM to 1 KB 2021-06-08 14:04:32 -04:00
bbracker
e7e4105931 * GPIO comprehensive testing 
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
 2021-06-08 12:32:46 -04:00
bbracker
4e765ee1c5 expanded GPIO testing and caught small GPIO bug 2021-06-03 10:03:09 -04:00
bbracker
bf6337f2f7 plic implementation optimizations 2021-05-19 18:10:48 +00:00
David Harris
afd6153044 Rolled back fflush on uart. Use -syncio in Modelsim command line instead. 2021-05-03 20:04:44 -04:00
David Harris
d07a7fd0f8 Flush uart print statements on \n 2021-05-03 19:51:51 -04:00
David Harris
93466a0b2a Flush uart print statements on \n 2021-05-03 19:41:37 -04:00
David Harris
58ce0fbbcc Flush uart print statements on \n 2021-05-03 19:37:45 -04:00
David Harris
233726e8d8 Flush uart print statements on \n 2021-05-03 19:25:28 -04:00
bbracker
182bfdbb0e rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
86946266cf thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
38236e9172 Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Ross Thompson
4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
bbracker
38017e6aae declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202 plic subword access compliance 2021-04-04 23:10:33 -04:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
bbracker
85363e941d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
David Harris
42275e92ed Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
bbracker
850a2e9329 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7 more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
0f4a231543 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Noah Boorstin
735c6789ea busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
Teo Ene
babe6ce9db Properly implemented the fix from commit 31c07b2adc 2021-02-28 22:22:04 -06:00
Noah Boorstin
f306d2d2e1 busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
6e70ae8b3d busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00