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Author SHA1 Message Date
Ross Thompson
7ff715f44f More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
600c18845f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 19:14:39 -06:00
Ross Thompson
829c6ea264 Added explainations of synthesis variables in README. 2022-02-09 18:47:20 -06:00
Ross Thompson
8a10198d43 Added saif to synthDC flow. 2022-02-09 18:42:48 -06:00
Ross Thompson
4fd0154d03 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
bbracker
fd4556393b rename dump-dts debug script 2022-02-10 00:10:09 +00:00
bbracker
7b52ff9fcf continue to rename devicetree to wally-virt 2022-02-10 00:08:28 +00:00
bbracker
3ebf6d7418 rename devicetree to wally-virt 2022-02-10 00:07:29 +00:00
Ross Thompson
02abb31f5a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:44:33 -06:00
Ross Thompson
ec9ac430cd Commented quit. 2022-02-09 16:44:26 -06:00
James E. Stine
186185ef8b Update on README.md for synthDC 2022-02-09 16:20:05 -06:00
Ross Thompson
74bccc468c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:11:31 -06:00
Ross Thompson
3bbc044d11 Added support for 90nm. 2022-02-09 16:06:27 -06:00
James E. Stine
2eef7ec0ee Add power analysis to synth.tcl 2022-02-09 16:04:20 -06:00
Ross Thompson
5a654a2874 Cleaned up synthesis flow. 2022-02-09 15:18:49 -06:00
Ross Thompson
380085ca20 Updated synthesis and Makefile to output into binned directories. 2022-02-09 15:06:42 -06:00
David Harris
793670d878 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-09 19:47:52 +00:00
David Harris
dbcad218dd Merged synthesiss scripts into main 2022-02-09 19:47:50 +00:00
bbracker
e9273c10ac minor interrupt syntax fix 2022-02-09 02:56:39 +00:00
bbracker
e157e89044 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-09 02:30:00 +00:00
bbracker
5669b9d1ca add tracegen support for interrupt parsing 2022-02-09 02:29:47 +00:00
Ross Thompson
7810a09782 Annotated the final changes required to move sram address off the critial path. 2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757 Cache cleanup write enables. 2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 15:43:18 -06:00
Ross Thompson
44d4e08009 Fixed debug2.xdc to match wally changes. 2022-02-08 15:23:44 -06:00
Ross Thompson
c2907ec0f4 Cleanup IFU. 2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67 rv32e works for now. Still need to optimize. 2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a Moved some muxes back into the bp. 2022-02-08 14:17:44 -06:00
David Harris
1479762ae9 RAM simplification 2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272 Temporary commit which gets the no branch predictor implementation working. 2022-02-08 14:13:55 -06:00
David Harris
510b47523a rv32e config update 2022-02-08 17:59:50 +00:00
Ross Thompson
853a7bba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 11:36:30 -06:00
Ross Thompson
8a2ee22395 Finished merge. 2022-02-08 11:36:24 -06:00
David Harris
e61883b922 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-08 16:41:13 +00:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
bbracker
b4d6cc49e6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-08 16:08:04 +00:00
Ross Thompson
e2191e3637 Preparing to make a major change to the cache's write enables. 2022-02-08 09:47:01 -06:00
David Harris
f00b3ac27e Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
76dccbad91 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
bbracker
7ea9b10309 update buildroot main.config to reflect most recent image build 2022-02-08 11:47:26 +00:00
bbracker
c12a8578a0 restore trace generation functionality for new setup 2022-02-08 11:45:42 +00:00
bbracker
b0fda60cf7 gitignore dtb's because we only care about dts's as being source files 2022-02-08 11:14:59 +00:00
bbracker
f94e5560ac add trimmed-down virt devicetree to repo for QEMU 2022-02-08 11:11:44 +00:00
David Harris
5216a96857 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-08 10:26:39 +00:00