David Harris
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8c6ddcc15b
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changed name to CORE-V-WALLY
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2023-01-11 15:15:08 -08:00 |
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David Harris
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3ea4dd4898
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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d1bfdddd8c
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Rename FP and FPU to F in signal names
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2023-01-11 11:46:36 -08:00 |
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David Harris
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15026f61f7
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FPU comments
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2023-01-11 11:31:28 -08:00 |
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David Harris
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654abcde61
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Replaced MDUE with IntDivE in FDIVSQRT
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2023-01-11 11:06:37 -08:00 |
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David Harris
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739c2c8322
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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David Harris
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33c910f952
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Remove unused signals
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2023-01-07 06:26:29 -08:00 |
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David Harris
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f8af51e07b
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Handle special case Int Div/Rem of |A| < |B| in a single cycle
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2023-01-01 13:54:01 -08:00 |
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David Harris
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6832b9d9f6
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config file, comment, postproc cleanup
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2022-12-31 05:20:56 -08:00 |
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Cedar Turek
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eef1d4dd66
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comment cleaning
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2022-12-30 11:11:34 -08:00 |
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Cedar Turek
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7e5cafeda3
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Described internal signals of fdivsqrt top
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2022-12-30 11:01:02 -08:00 |
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Cedar Turek
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8cb4a7a69a
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Commented fdivsqrt module
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2022-12-30 10:52:25 -08:00 |
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Cedar Turek
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3115df9380
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Begin commenting divsqrt
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2022-12-30 10:43:02 -08:00 |
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David Harris
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776f4714af
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Clean up names and comments in divsqrt
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2022-12-29 08:02:44 -08:00 |
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David Harris
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d59878a886
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Moved IDIV_ON_FP into conditional block in fdivsqrtpreproc
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2022-12-27 21:53:00 -08:00 |
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David Harris
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dfc0b5d1ad
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Removed MDUE from unnecessary places in fdivsqrt
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2022-12-27 10:42:40 -08:00 |
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Cedar Turek
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f48b7d7ef9
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fpu idiv working on all configs with 1 copy of radix 2!
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2022-12-26 23:18:28 -08:00 |
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Cedar Turek
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bebaf08bed
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took out otfc swap. updated postprocessing quotient/remainder logic for int div.
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2022-12-26 21:03:56 -08:00 |
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David Harris
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2de66e9eef
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Moved fdivsqrtexpcalc to its own file
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2022-12-26 08:45:43 -08:00 |
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cturek
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cc6f219bdd
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Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.
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2022-12-24 06:46:52 +00:00 |
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David Harris
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9e21358d75
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Removed unused signals from FPU
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2022-12-23 00:18:39 -08:00 |
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David Harris
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0a7ed944a5
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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56312cd0a6
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Clean up unused FPU signals
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2022-12-22 23:53:09 -08:00 |
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David Harris
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4d509f94ec
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FDIV merge
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2022-12-22 23:03:03 -08:00 |
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David Harris
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2d72bed1f4
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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cturek
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ccbad67497
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Added negative-result int diviison support in U and UM registers. 13 tests pass!
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2022-12-22 16:25:37 +00:00 |
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cturek
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80ca75e216
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Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.
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2022-12-22 05:44:55 +00:00 |
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cturek
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c3fdc0ab23
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Renamed signals to E and M stages, forwarded preprocessed n to fsm
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2022-12-22 00:43:27 +00:00 |
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Alessandro Maiuolo
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5a82898649
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Added NumZeroE, AZeroM, and BZeroM
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2022-12-18 20:02:40 -08:00 |
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cturek
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06c58f310d
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Added mux for integer special case, renamed signals to match pipelined stage
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2022-12-16 18:43:49 +00:00 |
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cturek
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d7571bb9b1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-12-16 03:41:39 +00:00 |
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David Harris
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4365c99b52
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Refactored stalls and flushes, including FDIV flush with FlushE
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2022-12-15 10:56:18 -08:00 |
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David Harris
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5f637ef4a7
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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cturek
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8829e627eb
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Fixed BZero and initU/initUM muxes
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2022-12-14 16:44:46 +00:00 |
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cturek
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f57211bb49
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Ross Thompson
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de99663b97
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Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214 .
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2022-12-04 00:01:58 +00:00 |
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cturek
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70b89e5214
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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cturek
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1f32603c30
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Added flops to preproc
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2022-12-02 20:31:08 +00:00 |
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David Harris
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d64cd715f9
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Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
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9c1b7e53e4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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cturek
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7140642c93
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Almost done with Int division
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2022-11-22 22:22:59 +00:00 |
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David Harris
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ddba68605e
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Renamed DivBusy to FDivBusyE in FPU
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2022-11-16 10:13:27 -08:00 |
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David Harris
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e008d663f4
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Moved DivStartE to fdivsqrtfsm
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2022-11-16 10:00:07 -08:00 |
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cturek
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74f58b5d89
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Added Quotient/Remainder calcs to normal termination
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2022-11-13 23:44:34 +00:00 |
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cturek
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b3bfdbad18
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Added flops for n and m, added B=0 signal
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2022-11-13 23:02:43 +00:00 |
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cturek
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9c70ab917c
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Added A<B signal to fdivsqrt, started postprocessing merge
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2022-11-13 22:40:26 +00:00 |
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cturek
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ff410cd849
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Added integer step counter to fsm
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2022-11-11 00:23:25 +00:00 |
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cturek
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1e927df1a0
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Added conditional OTFC swap for simplified int postprocessing
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2022-11-06 23:09:09 +00:00 |
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cturek
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333da5c945
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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cturek
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b893d9249d
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Added new macros for int div preprocessing, added p, n, and rightshiftx logic
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2022-11-06 21:53:48 +00:00 |
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