Ross Thompson
73ad5715f4
Cleanup IFU comments.
2022-01-14 15:06:30 -06:00
Ross Thompson
b8f4eb2997
Optimization in the ifu. Please note this optimization is not strictly correct,
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but is possible. See comments in the ifu source code for details.
2022-01-14 12:16:48 -06:00
Ross Thompson
2e8f5e06bd
More ifu cleanup.
2022-01-14 11:19:12 -06:00
Ross Thompson
3bec276862
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
James E. Stine
e0e30c1e9e
Update to TestFloat for scripts so can run automatically once
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TestFloat/Softfloat is compiled. Slight change to the README as well.
2022-01-14 09:25:37 -06:00
Ross Thompson
a973681a90
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7
Partial local dtim in lsu configuration.
2022-01-13 17:50:31 -06:00
David Harris
602867f54e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-13 21:46:00 +00:00
David Harris
7d13740a11
Mixed C and assembly language test cases; SRT initial version passing tests
2022-01-13 21:45:54 +00:00
Ross Thompson
e6e3b0607a
Merge branch 'testDivInterruptInterlock' into main
2022-01-13 11:21:48 -06:00
Ross Thompson
f870b8b3d3
Fixed interger divide so it can be interrupted.
2022-01-13 11:16:50 -06:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
Ross Thompson
a23e6efd5c
Fixed bug in the lsu's write back data. If an AMO was uncached it would not be corrected executed because the write data to the bus would not include the amoalu.
2022-01-12 17:41:39 -06:00
Ross Thompson
85b5dc08a8
Fixed support to allow spills and no icache.
2022-01-12 17:25:16 -06:00
Ross Thompson
e06fb923a1
Better solution to the integer divider interrupt interaction.
2022-01-12 14:22:18 -06:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
cd75bf98e1
If a trap occurs concurrent with a I/DTLB miss the interlock fsm incorrectly goes into the states to handle the TLB miss.
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This commit fixes this bug by keeping the interlock fsm in the T0_READY state on TrapM.
2022-01-12 14:17:16 -06:00
Ross Thompson
b294f1fbb0
Oups. My hack for DivE interrupt prevention was wrong.
2022-01-12 14:17:16 -06:00
Ross Thompson
459f4bd3b4
Hack "fix" to prevent interrupt from occuring during an integer divide.
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This is not the desired solution but will allow continued debuging of linux.
2022-01-12 14:17:16 -06:00
Ross Thompson
960af4b70f
Set rv32ic to not use icache.
2022-01-12 14:10:09 -06:00
Ross Thompson
f18684efbf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-12 13:29:19 -06:00
Ross Thompson
786a772444
Improve wavefile by adding performance counters.
2022-01-12 10:53:29 -06:00
Kip Macsai-Goren
c251144460
Fixed PMA regions, Added passing PMA tests to regression
2022-01-10 22:08:26 +00:00
David Harris
3a2b459439
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
401a5b1779
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
David Harris
0212260eef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
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only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
bea6d0856d
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
40af3abef9
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
c97572d209
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
c9c3bddc6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
08231d4e66
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
cb68548b88
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
fc4db84bbc
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
b3ebce0365
some FPU test fixes
2022-01-06 23:03:20 +00:00
