16 Commits

Author	SHA1	Message	Date
David Harris	c260354817	Removed unused UARCH configuration entries	2023-01-06 05:11:14 -08:00
Cedar Turek	f48b7d7ef9	fpu idiv working on all configs with 1 copy of radix 2!	2022-12-26 23:18:28 -08:00
David Harris	2457448e29	Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE	2022-12-15 08:23:34 -08:00
David Harris	33aca5d35e	Added IDIV_ON_FPU flag to control whether integer division uses FPU	2022-12-15 06:37:55 -08:00
Ross Thompson	f9ffcf377b	Reverted the IROM/DTIM address range modelsim assignment.	2022-11-30 17:13:33 -06:00
David Harris	76006825b3	Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding	2022-08-26 21:18:18 -07:00
David Harris	460a95f99b	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
David Harris	6409548c8b	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	906f6f2990	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
Ross Thompson	bd9401179d	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
Ross Thompson	b650d7e05a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	c6927d2ace	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Ross Thompson	856ac24686	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
slmnemo	7c019ea074	Removed references to initialization files	2022-06-23 16:50:27 -07:00
DTowersM	dd34f25ffd	changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability	2022-06-10 00:37:53 +00:00
Katherine Parry	cd8b2a2b98	added config rv64fpquad	2022-06-02 22:09:11 +00:00