Shriya Nadgauda
968994c04a
updated pipeline tests
2021-05-03 22:07:36 -04:00
Thomas Fleming
0254ca7bf6
Adjust attributes in PMA checker
2021-05-03 21:58:32 -04:00
Thomas Fleming
b7056c85bd
Get MMU tests working in OVPsim
2021-05-03 21:58:05 -04:00
David Harris
afd6153044
Rolled back fflush on uart. Use -syncio in Modelsim command line instead.
2021-05-03 20:04:44 -04:00
David Harris
603c7712a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:51:54 -04:00
David Harris
d07a7fd0f8
Flush uart print statements on \n
2021-05-03 19:51:51 -04:00
Elizabeth Hedenberg
a654b8a3d3
coremark update
2021-05-03 19:42:00 -04:00
David Harris
93466a0b2a
Flush uart print statements on \n
2021-05-03 19:41:37 -04:00
David Harris
e265aa4d41
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:37:56 -04:00
David Harris
58ce0fbbcc
Flush uart print statements on \n
2021-05-03 19:37:45 -04:00
Elizabeth Hedenberg
2d1d929485
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
2a33673e3c
coremark updates
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
b99fbc73f1
coremark update
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
7f5b8e63ed
Coremark objump push
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
463ba1a2be
coremark directory changes
2021-05-03 19:35:06 -04:00
David Harris
b66c7b81de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
233726e8d8
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
baf29454f1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Domenico Ottolia
0f10d577d2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:56:05 -04:00
Ross Thompson
82b4d42f32
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
5ab86a690b
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Thomas Fleming
ba1afec621
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:38:13 -04:00
Thomas Fleming
eda5a267ee
Implement PMP checker and revise PMA checker
2021-05-03 17:37:42 -04:00
Thomas Fleming
8dce32fd22
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Jarred Allen
7d509252a7
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
e145670b15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
cdb602c9ce
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
19a93345b5
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
David Harris
d7438929d4
Extended maximum signature length to 1M
2021-05-03 15:29:20 -04:00
Katherine Parry
ff5a809c26
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Thomas Fleming
cfe64e7c24
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
Ross Thompson
a54c231489
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
c643372e1d
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
bbracker
9ab714e636
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
c7b97d0339
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Ross Thompson
c0a4b7cb17
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
a37d9b5e8e
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
9bde239143
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
2368b58cc9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Noah Boorstin
b98bc89f76
ok should be the final parsing script change from me
2021-05-03 01:37:24 -04:00
Noah Boorstin
f6acec191a
buildroot: add one final utility script
2021-05-03 01:28:09 -04:00
Noah Boorstin
b32128465c
busybear: remove now unneeded hack for fixed CSR issue
2021-05-01 15:17:04 -04:00
Katherine Parry
db95151d8d
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
1fcd43e844
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Noah Boorstin
48d32c1daf
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Domenico Ottolia
d03ca20dc9
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Ross Thompson
818c0abc89
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Domenico Ottolia
61beedf275
Add .S files for new mcause and scause tests
2021-04-29 16:48:56 -04:00
