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Configurable RISC-V Processor
762 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
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7f38056879
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Ross Thompson 7f38056879 fixed subtle typo in icache fsm. Was messing up hit spill hit. 
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Created special test for driving the instruction spill error. 2021-04-08 15:05:08 -05:00
wally-pipelined fixed subtle typo in icache fsm. Was messing up hit spill hit. 2021-05-03 16:55:36 -05:00
.gitignore Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor