112 Commits

Author	SHA1	Message	Date
Ross Thompson	0d6ce1d459	Fixed bug with the performance counters not updating.	2022-12-24 14:24:17 -06:00
Ross Thompson	a2de53aeeb	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. ... Generate WFIStallM in the privileged unit rather than generate in hazard. Cleaned up the hazard cause logic to be consistent across all causes.	2022-12-23 15:10:37 -06:00
David Harris	0505f1fd37	Moved InstrValidNotFLushed to csr including InstrValidM	2022-12-23 00:27:44 -08:00
David Harris	3b1fe78bdc	Removed unused StallW from CSRs	2022-12-23 00:21:36 -08:00
David Harris	0a7ed944a5	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	2d72bed1f4	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
David Harris	d4bedca1bf	Code cleanup	2022-12-22 10:04:50 -08:00
David Harris	6d46261350	comment cleanup	2022-12-21 12:39:09 -08:00
David Harris	c7f3aae084	Only delegated bits of SIP are readable	2022-12-21 12:32:49 -08:00
Ross Thompson	c3b43b2fac	Waiting on fix for wally64periph uart test. ... would like to remove vectored interrupt adder.	2022-12-21 13:16:09 -06:00
Ross Thompson	0b4186f1e8	Vectored interrupts now require 64 byte alignment. ... Eliminates adder.	2022-12-21 12:05:49 -06:00
David Harris	5d91b3044f	Clean up vecgtored interrupts	2022-12-20 16:53:09 -08:00
David Harris	dd0a02f0c8	Converted tvecmux to structural	2022-12-20 16:24:04 -08:00
Ross Thompson	80be2e7be5	privileged pc mux cleanup.	2022-12-20 18:05:44 -06:00
Ross Thompson	97593e8a6f	Moved privileged pc logic into privileged unit.	2022-12-20 17:55:45 -06:00
Ross Thompson	65cbff9283	Changed long names of vectored pcm signals.	2022-12-20 17:01:20 -06:00
David Harris	caf457106a	Replaced || and && with single ops	2022-12-20 01:33:35 -08:00
David Harris	378c40002f	Clean up interrupt masking by Commit	2022-12-16 08:27:39 -08:00
Ross Thompson	1e2180ef98	Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.	2022-11-29 17:19:31 -06:00
Ross Thompson	56cc04316c	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00
Ross Thompson	638e506d0b	Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.	2022-09-28 17:39:51 -05:00
David Harris	113258a0d0	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
David Harris	c7ec9282fe	Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.	2022-06-02 14:18:55 +00:00
David Harris	aa7b0616e4	../src/privileged/csrc.sv	2022-05-31 21:12:17 +00:00
David Harris	788fe406b5	Moved delegation logic from privmode to trap to simplify interface	2022-05-31 14:58:11 +00:00
Ross Thompson	b853c4ba47	Updated fpga debugger.	2022-05-17 23:04:01 -05:00
David Harris	48e89485dd	Cause simplification	2022-05-12 23:47:21 +00:00
David Harris	9651ced9bb	Cause simplification	2022-05-12 23:39:10 +00:00
David Harris	2f283d9654	Cause simplification	2022-05-12 23:37:40 +00:00
David Harris	f5f1870077	Cause simplification	2022-05-12 23:33:35 +00:00
David Harris	5b7cccbc4b	Cause simplification	2022-05-12 23:33:22 +00:00
David Harris	581d841653	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	2a3f545e0c	Cause simplification	2022-05-12 23:27:02 +00:00
David Harris	c2b9fc0d8e	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	292d1f33da	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	662fffa830	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	16b86c199c	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	5f358a37c6	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	21ac969c7d	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	072c464dc1	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	14f9f41d2d	Partitioned privileged pipeline registers into module	2022-05-12 20:45:45 +00:00
David Harris	78448c7053	privileged cleanup	2022-05-12 20:21:33 +00:00
David Harris	dd61afb7dc	Formatting cleanup	2022-05-12 18:37:47 +00:00
David Harris	fde8375fbd	Moved Breakpoint and Ecall fault logic into privdec	2022-05-12 16:45:53 +00:00
David Harris	2ceed15bd5	Moved TLB Flush logic into privdec	2022-05-12 16:41:52 +00:00
David Harris	1e5d94bbab	Moved WFI timeout into privdec	2022-05-12 16:22:39 +00:00
David Harris	39ceb3a550	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	5670f77de2	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	4edf9b6355	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00