David Harris
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e2e63ca9a8
|
Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
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David Harris
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545d46acb9
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Simplifed mstatus.TSR handling
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2022-05-12 14:09:52 +00:00 |
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David Harris
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1e7401daa0
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Fixed typo in csrm
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2022-05-12 06:55:39 -07:00 |
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David Harris
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9999f69922
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Added MCONFIGPTR CSR hardwired to 0
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2022-05-12 04:31:45 +00:00 |
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David Harris
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8166fd772e
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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137b411bea
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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4f1b0fdc64
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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1a5bfcf078
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Fixed bug in delegated interrupts not being taken
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2022-05-08 04:50:27 +00:00 |
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David Harris
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a516f89f22
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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7f42ff06d2
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SFENCE.VMA should be illegal in user mode
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2022-05-05 15:15:02 +00:00 |
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David Harris
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f436e93fc5
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SFENCE.VMA should be illegal in user mode
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2022-05-05 14:59:52 +00:00 |
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David Harris
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9b7aab122e
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wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
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2022-05-05 14:37:21 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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David Harris
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4b91fddc0a
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Illegal instruction fault when running FPU instruction with STATUS_FS = 0
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2022-05-03 18:32:01 +00:00 |
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David Harris
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1166c40059
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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Kip Macsai-Goren
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33875b20b5
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fixed initial value, timing on fs bits changing after floating point instruction
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2022-04-25 19:17:29 +00:00 |
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David Harris
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0957b7040d
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Restored MPRV behavior per spec
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2022-04-25 14:52:18 +00:00 |
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David Harris
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1a8369b02b
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Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields
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2022-04-25 14:49:00 +00:00 |
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David Harris
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142636173e
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Added MTINST hardwired to 0, and added timeout of U-mode WFI
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2022-04-24 20:00:02 +00:00 |
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David Harris
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28e8aa4f97
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Fixed InstrMisalignedFaultM mtval
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2022-04-24 17:31:30 +00:00 |
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David Harris
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ffecdda6e6
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Improved priority order and mtval of traps to match spec
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2022-04-24 17:24:45 +00:00 |
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Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
|
Ross Thompson
|
a5d4e39e7d
|
Added back the instret counter to ILA.
|
2022-04-17 18:44:07 -05:00 |
|
David Harris
|
5bb521635e
|
Experiments with prefix comparator; minor fixes in WFI and testbench warnings
|
2022-04-17 21:43:12 +00:00 |
|
David Harris
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b4902a6ff9
|
First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
|
Ross Thompson
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f8bdb6db49
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-16 14:59:03 -05:00 |
|
Ross Thompson
|
bfc68bef69
|
Fixed possible bugs in LRSC.
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2022-04-16 14:45:31 -05:00 |
|
David Harris
|
6e16922aae
|
WFI should set EPC to PC+4
|
2022-04-14 17:05:22 +00:00 |
|
Ross Thompson
|
de868ef3a2
|
Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.
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2022-04-07 16:56:28 -05:00 |
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David Harris
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fb95767da0
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
|
Ross Thompson
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2376d66ec2
|
Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
|
Ross Thompson
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19a8df9739
|
Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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David Harris
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c4f2c6b110
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fpu compare simplification, minor cleanup
|
2022-03-29 17:11:28 +00:00 |
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Kip Macsai-Goren
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56a0542405
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made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
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2022-03-29 02:26:42 +00:00 |
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Kip Macsai-Goren
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709f8e6e0d
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fixed double multiplication on vectored interrupts
|
2022-03-28 19:12:31 +00:00 |
|
Ross Thompson
|
61c714ebe6
|
I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
|
2022-03-25 13:10:31 -05:00 |
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bbracker
|
4b376e2834
|
1st attempt at multiple channel PLIC
|
2022-03-24 17:08:10 -07:00 |
|
Ross Thompson
|
849707f161
|
Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.
|
2022-03-22 22:04:06 -05:00 |
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bbracker
|
11423d1d17
|
but apparently QEMU doesn't show UXL in SSTATUS
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2022-03-02 22:44:19 +00:00 |
|
bbracker
|
6d7bc928af
|
update SXL UXL bits in MSTATUS to match new QEMU trace
|
2022-03-02 22:15:57 +00:00 |
|
David Harris
|
131a1a4ded
|
Cleaned warning on HPTW default state
|
2022-02-16 17:40:13 +00:00 |
|
David Harris
|
72e83db9fe
|
removed csrn and all of its outputs because depricated
|
2022-02-15 19:59:29 +00:00 |
|
David Harris
|
d3034c4f01
|
Mostly removed N_SUPPORTED
|
2022-02-15 19:50:44 +00:00 |
|
David Harris
|
f734afb866
|
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
|
2022-02-15 19:48:49 +00:00 |
|
David Harris
|
1326ade1a0
|
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
|
2022-02-15 19:20:41 +00:00 |
|
David Harris
|
38bbe23d14
|
More config file cleanup; 32ic tests broken
|
2022-02-03 01:08:34 +00:00 |
|
David Harris
|
02071700d6
|
Removed Busybear dependencies
|
2022-02-02 20:28:21 +00:00 |
|
Ross Thompson
|
c2b2fae98d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-01-31 12:17:37 -06:00 |
|
David Harris
|
090533cfe9
|
Replaced || and && with | and &
|
2022-01-31 01:07:35 +00:00 |
|
Ross Thompson
|
06209c417f
|
Cleaned up the InstrMisalignedFault.
|
2022-01-28 13:19:24 -06:00 |
|
Ross Thompson
|
862bf2faae
|
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
|
2022-01-27 17:11:27 -06:00 |
|
Ross Thompson
|
e2343699d1
|
Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv
|
2022-01-20 16:39:54 -06:00 |
|
Ross Thompson
|
4a75e69457
|
Merged in the debug ila updates.
|
2022-01-18 17:29:21 -06:00 |
|
Ross Thompson
|
a5f773220e
|
Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.
|
2022-01-18 17:19:33 -06:00 |
|
Ross Thompson
|
e06fb923a1
|
Better solution to the integer divider interrupt interaction.
|
2022-01-12 14:22:18 -06:00 |
|
Ross Thompson
|
b294f1fbb0
|
Oups. My hack for DivE interrupt prevention was wrong.
|
2022-01-12 14:17:16 -06:00 |
|
Ross Thompson
|
459f4bd3b4
|
Hack "fix" to prevent interrupt from occuring during an integer divide.
This is not the desired solution but will allow continued debuging of linux.
|
2022-01-12 14:17:16 -06:00 |
|
Ross Thompson
|
73c488914f
|
Added icache access and icache miss to performance counters.
|
2022-01-09 22:56:56 -06:00 |
|
David Harris
|
120fb7863f
|
Reformatted MIT license to 95 characters
|
2022-01-07 12:58:40 +00:00 |
|
David Harris
|
c1d6550ccb
|
Removed generate statements
|
2022-01-05 14:35:25 +00:00 |
|
David Harris
|
b36ace221e
|
Renamed wally-pipelined to pipelined
|
2022-01-04 19:47:41 +00:00 |
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