bbracker
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5d60a3a9df
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update linux wave-do
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2021-10-07 19:15:11 -04:00 |
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bbracker
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f799a3f5e0
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more checkpoint reformatting
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2021-10-07 04:27:45 -04:00 |
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bbracker
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76b551cdb3
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don't log rf[0] to checkpoint
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2021-10-07 00:58:33 -04:00 |
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bbracker
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a5fbc36864
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update linker scripts to look for vmlinux files
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2021-10-06 16:51:31 -04:00 |
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David Harris
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36bbf0c502
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Divider cleaup
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2021-10-03 11:22:34 -04:00 |
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David Harris
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10ef563211
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Divider cleanup
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2021-10-03 11:16:48 -04:00 |
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David Harris
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78eba19a1f
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Replacing XE and DE with SrcAE and SrcBE in divider
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2021-10-03 11:11:53 -04:00 |
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David Harris
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48e33c79a9
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Reduced cycle count for DIVW/DIVUW by two
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2021-10-03 09:42:22 -04:00 |
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David Harris
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648cc8ef64
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Divider comments cleanup
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2021-10-03 01:12:40 -04:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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David Harris
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d468357c24
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-03 00:43:47 -04:00 |
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David Harris
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81601e26a3
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Divider cleanup
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2021-10-03 00:41:41 -04:00 |
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David Harris
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c690a863b5
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Added suffixes to more divider signals
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2021-10-03 00:32:58 -04:00 |
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bbracker
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7fdb0158d4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-03 00:30:49 -04:00 |
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bbracker
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bb868f7a37
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checkpoint generator bugfixes
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2021-10-03 00:30:04 -04:00 |
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David Harris
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0c08a7c05c
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More divider cleanup
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2021-10-03 00:20:35 -04:00 |
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David Harris
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5e6b2490cb
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Eliminated extra inversion for subtraction in divider
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2021-10-03 00:10:12 -04:00 |
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David Harris
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418e9cd6e6
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Added more pipeline stage suffixes to divider
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2021-10-03 00:06:57 -04:00 |
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David Harris
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b3bded9e6c
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Added more pipeline stage suffixes to divider
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2021-10-02 22:54:01 -04:00 |
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David Harris
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5db800fac3
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Divider mostly cleaned up
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2021-10-02 21:10:35 -04:00 |
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David Harris
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3a85c972b6
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Partial divider cleanup 3
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2021-10-02 21:00:13 -04:00 |
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David Harris
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5d64f04752
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Partial divider cleanup 2
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2021-10-02 20:57:54 -04:00 |
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David Harris
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f913305993
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Partial divider cleanup
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2021-10-02 20:55:37 -04:00 |
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David Harris
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afd6babc13
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Divider code cleanup
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2021-10-02 10:41:09 -04:00 |
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David Harris
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e33ef58e67
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Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
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2021-10-02 10:36:51 -04:00 |
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David Harris
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4926ae343a
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Divider code cleanup
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2021-10-02 10:13:49 -04:00 |
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David Harris
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852eb24731
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Moved negating divider otuput to M stage
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2021-10-02 10:03:02 -04:00 |
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David Harris
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9d63aa683f
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Moved muldiv result selection to M stage for performance
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2021-10-02 09:38:02 -04:00 |
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David Harris
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fbe6e41169
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Divide performs 2 steps per cycle
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2021-10-02 09:19:25 -04:00 |
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David Harris
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e11c565a6f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-30 23:15:34 -04:00 |
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bbracker
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6aa79657ed
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Revert "first attempt at verilog side of checkpoint functionality"
This reverts commit fec96218f6.
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2021-09-30 20:45:26 -04:00 |
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David Harris
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caa36f267d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-09-30 20:07:43 -04:00 |
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David Harris
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9d8e7f2714
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Integer Divide/Rem passing all regression.
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2021-09-30 20:07:22 -04:00 |
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David Harris
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760f4d66dd
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RV32 div/rem working signed and unsigned
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2021-09-30 15:24:43 -04:00 |
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David Harris
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42d573be57
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SRT Division unsigned passing Imperas tests
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2021-09-30 12:17:24 -04:00 |
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bbracker
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fec96218f6
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first attempt at verilog side of checkpoint functionality
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2021-09-28 23:17:58 -04:00 |
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bbracker
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a835572836
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first attemtpt at checkpoint infrastructure
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2021-09-28 22:33:47 -04:00 |
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bbracker
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7117c0493c
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condense testbench code; debug_level of 0 means don't check at all
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2021-09-27 03:03:11 -04:00 |
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Kip Macsai-Goren
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052b8b97fd
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updated pmp outputs with new exectuaion tests
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2021-09-24 16:30:16 -04:00 |
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Kip Macsai-Goren
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57fbd75ae3
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updated execute tests, light cleanup, privilege mode changes still need fix.
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2021-09-24 16:29:56 -04:00 |
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Kip Macsai-Goren
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9784fc139c
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updated test library to include: simpler execution tests, widths for each read/write, outputs for pmpaddr writes.
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2021-09-24 16:28:53 -04:00 |
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Kip Macsai-Goren
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9ace858a19
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completed and cleaned up pmp tests, including execute tests
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2021-09-24 16:18:44 -04:00 |
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bbracker
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3f96ff0ac0
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switch testbench-linux's interrupts from xcause to mip and improve warning messages
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2021-09-22 12:33:11 -04:00 |
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bbracker
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8b97f8154f
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update setup scripts to new testvector files
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2021-09-22 12:31:10 -04:00 |
|
Ross Thompson
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221dbe92b2
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Fixed the amo on dcache miss cpu stall issue.
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2021-09-17 22:15:03 -05:00 |
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Ross Thompson
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e16c27225b
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Finished adding the d cache flush. Required ensuring the write data, address, and size are
correct when transmitting to AHBLite interface.
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2021-09-17 13:03:04 -05:00 |
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Ross Thompson
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cfd522da6b
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The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
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2021-09-17 10:33:57 -05:00 |
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Ross Thompson
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0b1e59d075
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Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
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Ross Thompson
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615fd41e7b
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Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
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2021-09-16 18:32:29 -05:00 |
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Ross Thompson
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348187ea70
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Added counters to walk through d cache flush.
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2021-09-16 17:12:51 -05:00 |
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