slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Daniel Torres
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b726b05d61
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fixed wally rv32e tests, updated regression makefile to new testflow
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2022-07-22 17:09:46 -07:00 |
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Daniel Torres
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640c9562d3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 15:35:25 -07:00 |
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Daniel Torres
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e02c67ed5e
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fixed 32priv tests, now passing
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2022-07-22 15:35:20 -07:00 |
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Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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Daniel Torres
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d95b266d49
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changes to test.vh for compatability
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2022-07-22 15:00:48 -07:00 |
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Daniel Torres
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2bbfd67082
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added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
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2022-07-22 14:58:55 -07:00 |
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slmnemo
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44c30ec082
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fixed error in tests.vh
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2022-07-22 14:55:55 -07:00 |
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slmnemo
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170601af0b
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Added UART test to peripheral test
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2022-07-22 14:55:34 -07:00 |
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slmnemo
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840c40a7ab
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UART updates and PMA fix
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2022-07-22 14:49:03 -07:00 |
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Daniel Torres
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fbe3a1af12
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 13:52:19 -07:00 |
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Daniel Torres
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261b9aa5a1
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commented out embench test that should be commented out
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2022-07-22 13:52:13 -07:00 |
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slmnemo
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49329b3f42
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 12:36:06 -07:00 |
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slmnemo
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6d8988f71f
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Added test comments to reference output
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2022-07-22 12:35:59 -07:00 |
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slmnemo
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0d98ff74b4
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Added PLIC test to regression
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2022-07-22 12:35:37 -07:00 |
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Daniel Torres
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5d7171f6f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-22 11:16:09 -07:00 |
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Daniel Torres
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526f70e772
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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cturek
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338f44dfc8
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Square root negative exponent handling
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2022-07-22 16:45:19 +00:00 |
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slmnemo
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12c92a05ff
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Added new PLIC and UART tests
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2022-07-22 07:12:55 -07:00 |
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slmnemo
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49565f944c
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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David Harris
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07c946bb04
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Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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Daniel Torres
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28c61a2191
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changed gitignore, updated version of arch tests on main build
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2022-07-21 21:10:15 -07:00 |
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Daniel Torres
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f1578936b8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 20:59:01 -07:00 |
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Daniel Torres
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bd918d37ba
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added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
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2022-07-21 20:58:58 -07:00 |
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slmnemo
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99dcff80c9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-21 20:35:52 -07:00 |
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slmnemo
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bfa500234d
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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cturek
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c170a8d9b6
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Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder
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2022-07-22 01:27:08 +00:00 |
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cturek
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abe1ff906e
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Renamed variables, moved output handling to postprocessor, added remainder handling
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2022-07-21 20:45:08 +00:00 |
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Daniel Torres
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a17361870f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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d44ec059d0
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made makefile more specific, just incase future additions
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2022-07-21 12:50:02 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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e330a840b0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-21 19:38:15 +00:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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cturek
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ddc237f6bc
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Division working too
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2022-07-21 17:59:10 +00:00 |
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cturek
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9c694b887e
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Updated Radix2 Sqrt to follow new algorithm
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2022-07-21 17:36:21 +00:00 |
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Daniel Torres
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dad913cb82
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fixed gitmodules
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2022-07-21 10:15:13 -07:00 |
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Daniel Torres
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f33c6c9455
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 10:14:20 -07:00 |
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Daniel Torres
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e9aedfdc53
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changed the default branch of embench
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2022-07-21 10:14:05 -07:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Katherine Parry
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e8c9830b88
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turn off 2 word store durring non-fp instructions
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2022-07-20 21:57:23 +00:00 |
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Katherine Parry
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fb890d621d
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moved ctrl signal registers into fctrl, also a lot of code cleaning
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2022-07-20 02:27:39 +00:00 |
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cturek
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d7e90a7086
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divsqrt working for floating point
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2022-07-20 02:04:20 +00:00 |
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cturek
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f75d1c2eef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-20 02:00:50 +00:00 |
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cturek
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8e66b81821
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New radix-2 algorithm implemented and working
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2022-07-20 02:00:43 +00:00 |
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David Harris
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9d125addfa
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-20 01:49:36 +00:00 |
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David Harris
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4c740e1494
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Reordered embench Makefile to run size tests first
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2022-07-20 01:49:33 +00:00 |
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cturek
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db39a05abc
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small changes
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2022-07-20 01:36:25 +00:00 |
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Katherine Parry
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531829f7c8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-19 23:44:41 +00:00 |
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Katherine Parry
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afcddf7035
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oprimized zeros and replaced complex ?: with always_comb
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2022-07-19 23:44:37 +00:00 |
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