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Author SHA1 Message Date
Ross Thompson
72f77656a3 Fixed bug with instruction classification. The class decoder was incorretly labeling jalr acting as both jalr and jr (no link). 2021-05-24 12:37:16 -05:00
Ross Thompson
8bf411c640 Updated branch predictor tests/benchmarks. 2021-05-24 11:13:33 -05:00
James E. Stine
6f38b7633c Update header for FPadd 2021-05-24 08:28:16 -05:00
Katherine Parry
70968a4ec3 FSD and FLD imperas tests pass 2021-05-23 18:33:14 -04:00
bbracker
846553ac7d improved PLIC test organization 2021-05-21 15:13:02 -04:00
James E. Stine
e70136ec78 Minor testbench updates to rv64icfd 2021-05-21 09:41:21 -05:00
James E. Stine
23769e36a5 Update to testbench-imperase for rv64icfd 2021-05-21 09:28:44 -05:00
James E. Stine
fed3b30557 Update to FLD/FSD testbench 2021-05-21 09:26:55 -05:00
James E. Stine
c89d3e01bb Update to rv64icfd wally-config to run through FP tests 2021-05-21 09:22:17 -05:00
Katherine Parry
4db7f3065c FMV.D.X imperas test passes 2021-05-20 22:18:33 -04:00
Katherine Parry
06af239e6c FMV.D.X imperas test passes 2021-05-20 22:17:59 -04:00
bbracker
1d3db5ead5 small bit of busybear debug progress 2021-05-19 20:18:00 -04:00
bbracker
bf6337f2f7 plic implementation optimizations 2021-05-19 18:10:48 +00:00
bbracker
979a9bf037 commented out MSTATUS test 2021-05-19 12:38:01 -04:00
James E. Stine
304e70d3ae Update rv64icfd batch script 2021-05-18 16:01:53 -05:00
James E. Stine
44dc665fc5 Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA) 2021-05-18 13:48:44 -05:00
bbracker
e4d51ebef5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-18 14:33:40 -04:00
bbracker
c495fc71f1 changed lint script to use absolute path for verilator because cron jobs stink at using paths 2021-05-18 14:33:22 -04:00
David Harris
26531f2634 fixed rv64mmu makefile 2021-05-18 14:25:55 -04:00
David Harris
5da159d17e Removed rv64wally 2021-05-18 14:08:46 -04:00
David Harris
4d264c6f61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
 2021-05-18 14:01:19 -04:00
bbracker
a885d44129 commented changes to imperas makefiles 2021-05-18 13:34:48 -04:00
Katherine Parry
9464c9022d floating point infinite loop removed from imperas tests 2021-05-18 10:42:51 -04:00
bbracker
2feb9309bb script for running make and logging output 2021-05-17 22:12:18 -04:00
bbracker
02966dd649 changed makefiles so that make stops at bad source code that does not compile 2021-05-17 21:20:30 -04:00
bbracker
f00eb22700 fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions 2021-05-17 19:25:54 -04:00
bbracker
e4c90f503a regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench 2021-05-17 18:44:47 -04:00
David Harris
9901f54b15 Deleted vish_stacktrace 2021-05-17 18:39:01 -04:00
David Harris
4370699f3d Started MSTATUS tests 2021-05-17 18:37:56 -04:00
James E. Stine
e808b06b82 Forgot initialization config for div - apologies 2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
b818ce608a commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
Elizabeth Hedenberg
752fefd870 coremark commit ehedenberg final 2021-05-17 18:02:34 -04:00
James E. Stine
5506efc115 Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
James E. Stine
3d3e3434f6 Cleanup of regression 2021-05-17 16:58:15 -05:00
James E. Stine
daf780b9c2 Mod Imperas Testbench for updated Div/Rem 2021-05-17 16:56:30 -05:00
James E. Stine
865b3ee219 Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
Thomas Fleming
b9e099d53c Fix comment 2021-05-14 08:06:07 -04:00
Thomas Fleming
6aa04af38d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-14 07:40:08 -04:00
Thomas Fleming
ea4e76938e Remove busy-mmu and fix missing signal 2021-05-14 07:14:20 -04:00
Thomas Fleming
e27bc1cbf7 Clean up MMU code 2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg
170f072b52 pushing coremark to main branch 2021-05-11 21:33:39 -04:00
Elizabeth Hedenberg
fc69a0cac6 coremark integration into main 2021-05-11 21:33:38 -04:00
Jarred Allen
041149eaf7 Minor fixes in regression 2021-05-09 13:57:09 -04:00
Jarred Allen
c7f400262c Fix bug in regression script 2021-05-06 12:56:57 -04:00
Domenico Ottolia
e3624ab2e6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 20:22:31 -04:00
Domenico Ottolia
88ab07d456 Forgot to add csr permission tests to testbench 2021-05-04 20:20:22 -04:00
Jarred Allen
be029ba02c Clean up regression script and document it 2021-05-04 18:58:59 -04:00
ushakya22
682bc7b58e Added mip tests to testbench 2021-05-04 15:36:06 -04:00
Thomas Fleming
1ec6ad14f6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-05-04 15:22:21 -04:00
bbracker
8a7fc959eb small synthesis fixes 2021-05-04 15:21:01 -04:00