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Configurable RISC-V Processor
846 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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David Harris 4d264c6f61 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
riscv-coremark commit ehedenberg coremark 2021-05-17 18:02:35 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Created special test for driving the instruction spill error. 2021-04-08 15:05:08 -05:00
wally-pipelined Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-18 14:01:19 -04:00
.gitignore Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor