Ross Thompson
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84edb8b5d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-16 15:22:35 -06:00 |
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Ross Thompson
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bd7343b791
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Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
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2022-02-16 15:22:19 -06:00 |
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David Harris
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131a1a4ded
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Cleaned warning on HPTW default state
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2022-02-16 17:40:13 +00:00 |
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David Harris
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799736632b
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Register file comments about reset
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2022-02-16 17:21:05 +00:00 |
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Ross Thompson
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a64839d999
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-16 09:48:16 -06:00 |
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Skylar Litz
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03f23d2aaa
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update bugfinder script to new file organization
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2022-02-15 22:58:18 +00:00 |
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Kip Macsai-Goren
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6a76f40e26
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light cleanup
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
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05e944628d
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added high bit registers to CSR permission tests
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
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e16581d73d
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added CSR permission and minfor to 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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Kip Macsai-Goren
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943c4d9d7c
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merged test macros in with 32 bit tests
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2022-02-15 20:19:14 +00:00 |
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David Harris
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72e83db9fe
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removed csrn and all of its outputs because depricated
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2022-02-15 19:59:29 +00:00 |
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David Harris
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d3034c4f01
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Mostly removed N_SUPPORTED
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2022-02-15 19:50:44 +00:00 |
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David Harris
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f734afb866
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Just needed to recompile - all good. Now removed uretM because N-mode is depricated
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2022-02-15 19:48:49 +00:00 |
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David Harris
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1326ade1a0
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Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
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2022-02-15 19:20:41 +00:00 |
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David Harris
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bf1b02be92
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-15 19:01:42 +00:00 |
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David Harris
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8166e07004
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Sythesis uncertainty cleanup
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2022-02-15 19:01:38 +00:00 |
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Kip Macsai-Goren
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9ff4025844
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light cleanup for privileged tests
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2022-02-15 17:06:16 +00:00 |
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Kip Macsai-Goren
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985c20c961
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updated tests to use the combined library
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2022-02-15 17:06:16 +00:00 |
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Kip Macsai-Goren
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91915a808c
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Began to merge test-lib and test-macros into one file
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2022-02-15 17:06:16 +00:00 |
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Kip Macsai-Goren
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d47a731bda
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updated verify to only use comments with "#"
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2022-02-15 17:06:16 +00:00 |
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Ross Thompson
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6076f90bbc
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Cache mods to be consistant with diagrams.
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2022-02-14 12:40:51 -06:00 |
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David Harris
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dee2822359
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srt fixes
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2022-02-14 18:40:27 +00:00 |
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David Harris
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99aacd5aca
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srt batch files
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2022-02-14 18:37:46 +00:00 |
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ushakya22
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f4740cfda4
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bring branch back into main
Merge branch 'srt_division_with_unpacker' into main
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2022-02-14 18:25:34 +00:00 |
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ushakya22
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4170b54c28
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work in progress exponent handling
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2022-02-14 18:24:29 +00:00 |
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David Harris
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1d5c8a7b98
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t push
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-02-14 01:22:22 +00:00 |
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David Harris
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e6be19dfad
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Improved makefile and synthesis script for parallel processing, max optimization
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2022-02-14 01:22:17 +00:00 |
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Ross Thompson
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1bb4d46ac1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-13 18:21:15 -06:00 |
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Ross Thompson
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e852cb8a31
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Eliminated more ports in cacheway.
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2022-02-13 15:53:46 -06:00 |
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Ross Thompson
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1d7949513d
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More cache cleanup.
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2022-02-13 15:47:27 -06:00 |
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Ross Thompson
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7ffbc6b2ab
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Changed names of signals in cache.
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2022-02-13 15:06:18 -06:00 |
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Ross Thompson
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a5ad4331ec
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More cache cleanup.
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2022-02-13 12:38:39 -06:00 |
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ushakya22
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f87667d120
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Added unpacker into testbench for srt
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2022-02-12 22:05:18 +00:00 |
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David Harris
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0399a63b48
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Enbled multicore synthesis
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2022-02-12 06:44:58 +00:00 |
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David Harris
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b360e7b941
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Synthesis cleanup
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2022-02-12 06:25:12 +00:00 |
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David Harris
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a34cbdb7d0
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Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
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2022-02-12 05:50:34 +00:00 |
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Ross Thompson
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dd944265aa
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Formating improvements to cache.
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2022-02-11 23:10:58 -06:00 |
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Ross Thompson
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bf173b035c
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More cache simplifications.
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2022-02-11 22:54:05 -06:00 |
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Ross Thompson
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16abe90a0d
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Reduced seladr to 1 bit as second bit is same as selflush.
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2022-02-11 22:41:36 -06:00 |
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Ross Thompson
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b11e9eca7b
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Reduced complexity of the address selection during flush.
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2022-02-11 22:27:27 -06:00 |
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Ross Thompson
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1255e82154
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Removed redundant signals from cache.
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2022-02-11 22:23:47 -06:00 |
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Ross Thompson
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52894a7a4f
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Cache fsm simplifications.
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2022-02-11 15:16:45 -06:00 |
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Ross Thompson
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e2e0a4f595
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Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
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2022-02-11 15:09:00 -06:00 |
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Ross Thompson
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0f2ac0cb24
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Simplified cache fsm.
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2022-02-11 14:54:57 -06:00 |
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Ross Thompson
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d00d66409d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-11 14:00:13 -06:00 |
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Ross Thompson
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1c83914662
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Fixed bug.
It was possible for DTLBMissM to prevent a dcache flush.
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2022-02-11 14:00:01 -06:00 |
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Ross Thompson
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5394e79ad7
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Fixed ila's config.
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2022-02-11 13:58:45 -06:00 |
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Ross Thompson
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33beaa4593
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Updates to linux wave.
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2022-02-11 13:28:18 -06:00 |
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Ross Thompson
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d9f77d3659
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Updated linux wave.
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2022-02-11 13:15:42 -06:00 |
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Ross Thompson
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1a1629c62f
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linux wave cleanup.
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2022-02-11 10:48:45 -06:00 |
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