Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
635 Commits 14 Branches 1 Tag 31 MiB
532c8771ba
Commit Graph

88 Commits

Author SHA1 Message Date
Ross Thompson
532c8771ba major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Ross Thompson
f3093ac612 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Jarred Allen
81c02bda55 Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
Jarred Allen
3717699ad9 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Jarred Allen
892dfd5a9b More icache bugfixes 2021-04-14 19:03:33 -04:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
Jarred Allen
39bf2347bc Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Jarred Allen
0290568a52 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
ba95557c44 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
0f8fe8fb3b Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
827993598d Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Jarred Allen
6ce52f9b80 Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
f9cf05a7d4 Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
c5f99c4a34 Revert "Change flop to listen to StallF" 
This reverts commit c8028710a5.
 2021-03-20 17:34:19 -04:00
Jarred Allen
c8028710a5 Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00