Teo Ene 1018a10625 Various code syntax changes to bring HDL to a synthesizable level		2021-04-13 11:27:12 -05:00
..
bpred.sv	Switched to gshare from global history.	2021-03-18 16:05:59 -05:00
BTBPredictor.sv	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
decompress.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
globalHistoryPredictor.sv	Fixed minor bug with the size of gshare.	2021-03-18 16:00:09 -05:00
gshare.sv	Switched to gshare from global history.	2021-03-18 16:05:59 -05:00
icache.sv	Various code syntax changes to bring HDL to a synthesizable level	2021-04-13 11:27:12 -05:00
ifu.sv	Implement support for superpages	2021-04-08 02:44:59 -04:00
RAsPredictor.sv	RAS needs to be reset or preloaded. For now I just reset it.	2021-02-19 20:09:07 -06:00
satCounter2.sv	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.	2021-02-15 14:51:39 -06:00
SramModel.sv	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
twoBitPredictor.sv	Fixed forwarding around the 2 bit predictor.	2021-03-04 13:01:41 -06:00