Ross Thompson
3adc0d43e7
Prepared the ifu and icache for moving spills to ifu.
2022-01-03 17:09:36 -06:00
Ross Thompson
e0c310fea7
Fixed a bug where the instruction fetch got out of sync with the icache.
2022-01-03 13:27:15 -06:00
David Harris
d909e8f371
Replaced && and || with & and | in non-fp files per new style guidelines
2022-01-02 21:47:21 +00:00
Ross Thompson
b6fbc4a1e3
Added mux to select between uncache instruction requests and cached instructions requests.
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Cacheless design almost works with the exception of compressed instructions.
2021-12-30 18:09:37 -06:00
Ross Thompson
5904bc68c7
Patched up the linux-wave.do file.
2021-12-30 17:53:43 -06:00
Ross Thompson
6c45da022b
Progress on non dcache mode working.
2021-12-30 15:51:07 -06:00
Ross Thompson
c79e14fec5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
b6c9d01f8b
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
David Harris
2327f4b6bf
Added names to generate blocks
2021-12-30 20:55:48 +00:00
Ross Thompson
86514a6a23
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
Ross Thompson
9bcb105aa4
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
Ross Thompson
d50a65720d
More name cleanup in caches.
2021-12-30 09:18:16 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
8b97aaac3e
Fixed complex bug where FENCE is instruction class miss predicted as a taken branch.
2021-12-21 11:29:28 -06:00
Ross Thompson
3f62a64056
Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.
2021-12-20 23:45:55 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
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This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
David Harris
aebd746e71
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
865d5ce0b1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
9886ed3028
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
kwan
5164129172
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
05a838aee2
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
koooo142857
33f5de0f5c
aligned all files in ifu folder
2021-10-27 12:43:55 -07:00
David Harris
c9e9cd4a60
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
2cfbd888fd
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
62a23fe878
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
33358d101e
Lint cleanup: ahblite, ifu, hart
2021-10-23 10:12:33 -07:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
dac93bb366
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
c69a5dc8a6
fixed issue with tlbflush remaining high during a stalled sfence instruction
2021-07-21 17:43:36 -04:00
Ross Thompson
4d53b9002f
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
863e6e72d6
hptw: Propagating PageTableEntryF removal through IFU
2021-07-17 15:04:39 -04:00
David Harris
b65788d165
Replaced separate PageTypeF and PageTypeM with common PageType
2021-07-17 02:31:23 -04:00
Ross Thompson
e5d624c1fa
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Ross Thompson
3e57c899a2
Partially working changes to support uncached memory access. Not sure what CommitedM is.
2021-07-13 17:24:59 -05:00
Ross Thompson
93aa39ca31
completed read miss branch through dcache fsm.
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The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
Ross Thompson
3345ed7ff4
Merged several of the load/store/instruction access faults inside the mmu.
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Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
2021-07-06 13:43:53 -05:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
80666f0a71
Added ASID & Global PTE handling to TLB CAM
2021-07-04 17:52:00 -04:00
David Harris
7e22ae973e
Fixed MPRV and MXR checks in TLB
2021-07-04 13:20:29 -04:00
David Harris
67e191c6f3
Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
2021-07-04 11:39:59 -04:00
David Harris
1fa4abf7b6
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
