David Harris
b5d2bbe7ca
changed always_ff to always in sram1p1rw to fix testbench complaint
2022-09-25 19:56:40 -07:00
Ross Thompson
6a6686a34b
Removed the write first sram model.
2022-09-22 16:12:08 -05:00
Ross Thompson
29087812e1
Solved the sram write first / read first issue. Works correctly with read first now.
2022-09-22 14:16:26 -05:00
Ross Thompson
cdc80c1f28
Moved other SRAMs to generic/mem.
2022-09-21 12:36:03 -05:00
Ross Thompson
427db1f55f
Renamed brom1p1r to rom1p1r.
...
removed used file bram2p1r1w.sv.
2022-09-21 12:31:20 -05:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
Ross Thompson
b2f4d4aaa7
Added chip enables to sram.
2022-09-20 10:49:14 -05:00
David Harris
f628622ea0
Factored out aplusbeq0 unit
2022-09-07 11:36:35 -07:00
Ross Thompson
6685b0563e
James found a bug in synchronizer. Was not actually back to back flip flops.
2022-09-06 15:06:54 -05:00
Ross Thompson
2aa5886769
Fixed brom1p1r.sv to have fpga preload.
2022-09-02 15:49:50 -05:00
Ross Thompson
559e093ab5
Fixed up FPGA constraints.
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Added back in the fpga boot rom preload.
2022-09-02 13:54:35 -05:00
David Harris
24ce72f0a2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 09:52:49 -07:00
Ross Thompson
72b886ec8f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 09:03:34 -05:00
Ross Thompson
bc0edc7bdf
Updated ila signals.
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Improve fpga wave config.
added back in the fpga preload.
2022-08-25 09:03:29 -05:00
David Harris
b9dc8d9e33
Cleanup typos
2022-08-25 04:32:19 -07:00
David Harris
fe3147806d
removed simpleram and modified dtim to use bram1p1rw
2022-08-25 03:39:57 -07:00
David Harris
e6077f1f16
Added ROM module and moved memories into generic/mem
2022-08-24 17:03:22 -07:00
Ross Thompson
012559169b
Fixed lint errors with bram wrapper.
2022-08-24 13:19:23 -05:00
David Harris
e2138d8d0f
bram synthesis test
2022-08-23 19:34:45 -07:00
Ross Thompson
cd0da2e3b3
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
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Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
David Harris
1404d1c248
moved CSA to generic
2022-08-22 08:41:23 +00:00
Katherine Parry
e05b2a07d2
removed warnings and took a mux out of the critical path
2022-07-12 18:32:17 -07:00
Katherine Parry
41c16be012
srt divider merged into fpu
2022-07-07 16:01:33 -07:00
Madeleine Masser-Frye
846f12aa2e
new priority onehot module for better area/time
2022-07-06 00:08:59 +00:00
Katherine Parry
010a05f583
added missing files
2022-07-03 21:40:47 -07:00
slmnemo
ded2631567
Removed big64.txt reference, fixing a warning
2022-06-23 14:39:53 -07:00
David Harris
3c8eafc8ee
Cleaned bram interface
2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378
Added ahbapbbridge and cleaning RAM
2022-06-08 01:31:34 +00:00
Katherine Parry
e42afbfb30
paramerterized some small fma units
2022-06-01 23:34:29 +00:00
Katherine Parry
4ed7933aa3
added unpackinput.sv
2022-05-31 16:18:50 +00:00
Katherine Parry
95b506c5e0
some optimizations in unpacker
2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe
moved lzc to generic and small optimizations on fcvt
2022-05-27 09:04:02 -07:00
Ross Thompson
91e99f0d34
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-04-04 10:56:10 -05:00
Ross Thompson
b77201143f
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
2022-04-04 10:38:37 -05:00
Ross Thompson
48c49802b2
Fixed linting issues.
2022-04-01 15:20:45 -05:00
Ross Thompson
88c5cdc873
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-31 11:39:41 -05:00
Ross Thompson
bf9683f0d2
Forced to go back to hard coded preload.
2022-03-31 11:39:37 -05:00
Ross Thompson
285fc6fd4d
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
f52ab01362
Partial cleanup of memories.
2022-03-30 11:09:21 -05:00
Ross Thompson
839bede656
Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
2022-03-30 11:04:15 -05:00
Ross Thompson
66e9380cfb
Partial fix to allow byte write enables with fpga and still get a preload to work.
2022-03-29 19:12:29 -05:00
Ross Thompson
6d914def08
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
63b1ea88c9
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
396c97fc36
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
David Harris
1479762ae9
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
9da1ed4ed9
simpleram simplification
2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e
simpleram address simplification
2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a
simpleram address simplification
2022-01-25 18:00:50 +00:00
