58 Commits

Author	SHA1	Message	Date
David Harris	6a555032eb	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
Ross Thompson	9982549057	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	07425369fc	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
Ross Thompson	a973681a90	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	2b4c81fe98	Fixed unpacking bug; regression runs again	2022-01-06 18:22:30 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00