bbracker
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d3059dd04c
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fix UART RX FIFO bug where tail pointer can overtake head pointer
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2021-07-22 02:09:41 -04:00 |
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bbracker
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57a2917997
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make address translator signals visible in waveview
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2021-07-21 20:07:49 -04:00 |
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bbracker
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cd469035be
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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bbracker
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e4a50a5bb8
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change memread testvectors to not left-shift bytes and half-words
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2021-07-18 21:49:53 -04:00 |
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bbracker
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5e9dcb3f1c
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linux testbench progress
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2021-07-18 18:47:40 -04:00 |
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bbracker
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4a3503281f
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swapped out linux testbench signal names
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2021-07-17 14:46:18 -04:00 |
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bbracker
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01ca22af49
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changed stop of linux boot from arch_cpu_idle to do_idle
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2021-07-16 12:27:15 -04:00 |
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Katherine Parry
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36f59f3c99
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
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David Harris
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5f91b339aa
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Added F_SUPPORTED flag to disable floating point unit when not in MISA
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2021-07-05 10:30:46 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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13cf7c0934
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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be962cb1ff
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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David Harris
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a514554eeb
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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bbracker
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dc26f2a6d0
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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c77aabdc6f
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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d62d9a7aac
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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bbracker
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5b96f7fbd7
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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4e765ee1c5
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expanded GPIO testing and caught small GPIO bug
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2021-06-03 10:03:09 -04:00 |
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bbracker
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2c77a13c08
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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bbracker
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846553ac7d
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improved PLIC test organization
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2021-05-21 15:13:02 -04:00 |
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Katherine Parry
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06af239e6c
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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1d3db5ead5
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small bit of busybear debug progress
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2021-05-19 20:18:00 -04:00 |
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James E. Stine
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865b3ee219
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Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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Thomas Fleming
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cfe64e7c24
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-05-03 14:02:19 -04:00 |
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bbracker
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9ab714e636
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small rv64 plic test bugfix
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2021-05-03 10:06:44 -04:00 |
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Thomas Fleming
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6e5fc107d9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-29 16:30:00 -04:00 |
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Jarred Allen
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ebd9c0ee29
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Remove signal which no longer exists from default waves, so sim-wally works
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2021-04-29 14:41:10 -04:00 |
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Thomas Fleming
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c62fdfb7b3
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Remove unused waves from .do files
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2021-04-29 02:19:46 -04:00 |
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Noah Boorstin
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0324329ed9
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linux: start using internal branch predictor signal
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2021-04-26 14:34:38 -04:00 |
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Ross Thompson
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8e5409af66
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Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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bbracker
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1cc0dcc83f
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progress on bus and lrsc
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2021-04-26 07:43:16 -04:00 |
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bbracker
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a3487a9e47
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do script refactor
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2021-04-24 09:32:09 -04:00 |
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Jarred Allen
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850f728cc7
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Merge branch 'main' into cache
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2021-04-19 00:05:23 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Jarred Allen
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d99b8f772e
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Merge from branch 'main'
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2021-04-08 17:19:34 -04:00 |
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bbracker
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755e2e5771
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merge testbench
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2021-04-08 14:28:01 -04:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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James E. Stine
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cff08adc3a
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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ushakya22
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6b9ae41302
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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Jarred Allen
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631454ccf9
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Merge branch 'cache2' into cache
Conflicts:
wally-pipelined/testbench/testbench-imperas.sv
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2021-03-30 13:32:33 -04:00 |
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Jarred Allen
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7ca57cc4fc
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/regression/wave-dos/ahb-waves.do
wally-pipelined/src/ifu/ifu.sv
wally-pipelined/testbench/testbench-busybear.sv
wally-pipelined/testbench/testbench-imperas.sv
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2021-03-30 12:55:01 -04:00 |
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Jarred Allen
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39bf2347bc
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Fix error when reading an instruction that crosses a line boundary
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2021-03-25 18:47:23 -04:00 |
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ShreyaSanghai
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139c2076a1
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Removed PCW and InstrW from ifu
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2021-03-26 01:53:19 +05:30 |
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Jarred Allen
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3b4f0141f4
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Begin work on compressed instructions
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2021-03-25 14:43:10 -04:00 |
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Jarred Allen
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0290568a52
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Make cache output NOP after a reset
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2021-03-25 13:18:30 -04:00 |
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Jarred Allen
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602271ff7b
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rv64i linear control flow now working
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2021-03-25 13:02:26 -04:00 |
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Jarred Allen
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0d05c51af9
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Remove deleted signal from waves
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2021-03-23 14:17:17 -04:00 |
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Jarred Allen
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b63bfc7afa
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Fix conflicts in ahb-waves that snuck through manual merging
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2021-03-20 17:16:50 -04:00 |
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Jarred Allen
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279c09b27c
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Merge changes from main
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2021-03-18 18:58:10 -04:00 |
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