Elizabeth Hedenberg
2d1d929485
coremark print statment
2021-05-03 19:35:08 -04:00
Elizabeth Hedenberg
2a33673e3c
coremark updates
2021-05-03 19:35:07 -04:00
Elizabeth Hedenberg
463ba1a2be
coremark directory changes
2021-05-03 19:35:06 -04:00
David Harris
b66c7b81de
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 19:29:01 -04:00
David Harris
233726e8d8
Flush uart print statements on \n
2021-05-03 19:25:28 -04:00
Ross Thompson
baf29454f1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:57:36 -05:00
Domenico Ottolia
0f10d577d2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-03 17:56:05 -04:00
Ross Thompson
82b4d42f32
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 16:56:00 -05:00
Ross Thompson
7f38056879
fixed subtle typo in icache fsm. Was messing up hit spill hit.
...
I believe the mibench qsort benchmark runs after this icache fix.
2021-05-03 16:55:36 -05:00
Domenico Ottolia
5ab86a690b
Fix bug that caused stvec to get the wrong value
2021-05-03 17:54:57 -04:00
Jarred Allen
7d509252a7
Add lint to regression
2021-05-03 17:32:05 -04:00
Ross Thompson
e145670b15
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 14:53:54 -05:00
Ross Thompson
cdb602c9ce
Removed combinational loops between icache and PMA checker.
2021-05-03 14:51:25 -05:00
Ross Thompson
19a93345b5
Reduced icache to 1 port memory.
2021-05-03 14:47:49 -05:00
David Harris
d7438929d4
Extended maximum signature length to 1M
2021-05-03 15:29:20 -04:00
Katherine Parry
ff5a809c26
fpu warnings fixed/commented
2021-05-03 19:17:09 +00:00
Ross Thompson
a54c231489
Eliminated extra register and fixed ports to icache.
...
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
bbracker
c643372e1d
merge conflict resolved -- Ross and I made the same fix
2021-05-03 10:10:42 -04:00
bbracker
9ab714e636
small rv64 plic test bugfix
2021-05-03 10:06:44 -04:00
Ross Thompson
c7b97d0339
Added back in function name to wave.do
2021-05-03 09:04:48 -05:00
Ross Thompson
c0a4b7cb17
Fixed typo in ifu for bypassing branch predictor.
...
Fixed missing signal name in local history predictor.
2021-05-03 08:56:45 -05:00
David Harris
a37d9b5e8e
Fixed lint error in div
2021-05-03 09:26:12 -04:00
bbracker
9bde239143
ifu lint fixes
2021-05-03 09:25:22 -04:00
bbracker
2368b58cc9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-03 09:23:52 -04:00
Noah Boorstin
b32128465c
busybear: remove now unneeded hack for fixed CSR issue
2021-05-01 15:17:04 -04:00
Katherine Parry
db95151d8d
fpu imperas tests run
2021-05-01 02:18:01 +00:00
bbracker
1fcd43e844
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Noah Boorstin
48d32c1daf
rollback regression to 400k instrs for busybear
2021-04-29 20:59:30 -04:00
Domenico Ottolia
d03ca20dc9
Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
2021-04-29 20:42:14 -04:00
Ross Thompson
818c0abc89
Fixed memory size in configs for rv32ic and rv64ic.
...
Removed warning on call to $fscanf.
2021-04-29 17:36:46 -05:00
Domenico Ottolia
c60c4f4adc
Minor improvements to scause test
2021-04-29 16:48:07 -04:00
Domenico Ottolia
c8a81779ca
Add machine-mode timer interrupts to mcause tests
2021-04-29 16:39:18 -04:00
Domenico Ottolia
6fc04768f5
Same but don't break sim-wally this time
2021-04-29 15:33:27 -04:00
Domenico Ottolia
7ae5d4d11e
Add more exceptions to medeleg tests
2021-04-29 15:32:13 -04:00
ushakya22
9dfbfd5772
fix to pcm bug
2021-04-29 15:21:08 -04:00
ushakya22
77210527c1
Working MIE timer tests
2021-04-29 15:19:43 -04:00
Domenico Ottolia
4fae8088e3
Add medeleg tests
2021-04-29 15:02:36 -04:00
Jarred Allen
bf54c9b0b2
Enhance lint-wally functionality
2021-04-29 14:48:41 -04:00
Jarred Allen
ebd9c0ee29
Remove signal which no longer exists from default waves, so sim-wally works
2021-04-29 14:41:10 -04:00
Jarred Allen
8fd9cc679b
Fix compile error in branch predictor
2021-04-29 14:36:56 -04:00
Shreya Sanghai
1e57c6bb92
fixed bug in gshare, global and local history BP
2021-04-29 06:14:32 -04:00
Noah Boorstin
a4dad3403e
same but do that right this time
2021-04-28 14:27:28 -04:00
Domenico Ottolia
60dc6aaf48
Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests
2021-04-27 21:47:38 -04:00
Noah Boorstin
44606b6c19
busybear: respect branch predictor disable config
2021-04-27 15:52:18 -04:00
Ross Thompson
8ae28e7887
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Noah Boorstin
ff1a6b63ed
ok but do that better
2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9
linux: start using internal branch predictor signal
2021-04-26 14:34:38 -04:00
Ross Thompson
afbb100860
Fixed issue with not saving the first cache block read on a miss spill.
2021-04-26 12:57:34 -05:00
