bbracker
290b3424e5
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31
Add tests for scause and ucause
2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Domenico Ottolia
eb9e1843fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 16:57:27 -04:00
Domenico Ottolia
531423d7e1
Add 32 bit privileged tests
2021-04-15 16:55:39 -04:00
Teo Ene
2814579f30
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6
Quick fix to ahblite missing default statement done in class :)
2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/mmu/priority_encoder.sv
2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb
Change priority encoder to avoid extra assignment
2021-04-15 16:17:35 -04:00
Teo Ene
e3deb49b75
Small update to synth scripts
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Writes out corrent timing reports
2021-04-15 14:24:39 -05:00
Domenico Ottolia
aa74b14314
Fix bug in device/rv32p/Makefile.include so that 32-bit privileged tests will run
2021-04-15 14:50:03 -04:00
Thomas Fleming
ff9f1e5e72
Connect tlb and icache properly
2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf
Temporary change to mmu/priority_encoder.sv
...
Necessary to get synth working
Original HDL is still there, just commented out
2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df
integraded the FMA into the FPU
2021-04-15 18:28:00 +00:00
Ross Thompson
87b716170c
Merge branch 'bpfixes' into main
2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e
Cherry Pick merge of Shreya's localhistory predictor changes into main.
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fixed minor bugs in localHistory
2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479
added localHistoryPredictor
2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea
fixed bugs in global history to read latest GHRE
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Cherry pick Shreya's commits into main branch.
2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b
csri lint improvement
2021-04-15 09:05:53 -04:00
David Harris
be07768fbb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-14 23:41:23 -04:00
David Harris
8c1ef5f36c
Deleted extraneous exe2memfile.pl
2021-04-14 23:41:15 -04:00
Thomas Fleming
3c49fd08f6
Remove imem from testbenches
2021-04-14 20:20:34 -04:00
bbracker
8f7ddcfdff
rv64 interrupt servicing
2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab
busybear: use (slightly) less terrible verilog
2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41
busybear testbench updates
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start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic
I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Thomas Fleming
7d2d6823f1
Fix mmu lint errors
2021-04-13 19:19:58 -04:00
Thomas Fleming
e7286caec9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-13 17:56:56 -04:00
David Harris
c7c5b803e3
Updated risdvOVPsimPlus with symlink
2021-04-13 17:53:16 -04:00
Thomas Fleming
7f4e763a41
Update virutal memory tests
2021-04-13 17:17:08 -04:00
Thomas Fleming
0a9b208729
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-04-13 17:15:10 -04:00
Katherine Parry
ef011496a7
Various bugs fixed in FMA
2021-04-13 18:27:13 +00:00
Thomas Fleming
09c9c49541
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806
Add lru algorithm to TLB
2021-04-13 13:37:24 -04:00
Teo Ene
03bb37a849
Fixed synthesis log error caused by typo in synthesis script
2021-04-13 12:12:36 -05:00
Teo Ene
a426b3f199
Changed default target synth frequency
2021-04-13 11:48:30 -05:00
Teo Ene
1018a10625
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
Ross Thompson
35f8b4f74f
Fixed minor bug in muldiv which corrects the lint error.
2021-04-09 10:56:31 -05:00
ushakya22
99f2d24e05
Latest IE tests with timer interupts
2021-04-08 17:53:39 -04:00
bbracker
1ee8feffe5
integrated peripheral testing into existing workflow
2021-04-08 15:31:39 -04:00
bbracker
005f838b8d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:28:25 -04:00
bbracker
755e2e5771
merge testbench
2021-04-08 14:28:01 -04:00
Katherine Parry
b7ebfd66ed
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 18:06:51 +00:00
David Harris
8549e457c1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 14:04:09 -04:00
David Harris
6b2868a8c7
restored testbench-imperas.sv
2021-04-08 14:04:01 -04:00
Katherine Parry
2ee015d53e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-04-08 18:03:57 +00:00
Katherine Parry
f4cb92ae71
fixed FPU lint warnings
2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af
fixed FPU lint warnings
2021-04-08 17:55:25 +00:00
