Ross Thompson
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026071e247
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Merge branch 'imperas'
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2023-01-31 12:46:22 -06:00 |
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Ross Thompson
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f6aafd6bad
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Fixed bug with the new csr.
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2023-01-28 17:56:56 -06:00 |
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Ross Thompson
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6371d91b37
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Added another performance counter to track overall branch miss-predictions.
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2023-01-28 17:50:46 -06:00 |
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Ross Thompson
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4fa2dcc2a5
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Changed the performance counters to track different data.
Now rather than tracking jump(r) we track jump(r) and taken branches.
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2023-01-26 13:21:28 -06:00 |
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Ross Thompson
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626bcd8608
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Removed mark_debug from all source code.
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2023-01-20 18:47:36 -06:00 |
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Ross Thompson
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7c4eaa1ca6
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Found a potential issue with mstatush when XLEN = 64.
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2023-01-16 13:57:28 -06:00 |
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David Harris
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efe7e88258
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csr cleanup
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2023-01-13 22:12:06 -08:00 |
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David Harris
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90e7aa2d50
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csr cleanup
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2023-01-13 21:29:03 -08:00 |
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David Harris
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9526479782
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csr cleanup
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2023-01-13 21:25:55 -08:00 |
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David Harris
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c9c174de49
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csr cleanup
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2023-01-13 21:09:29 -08:00 |
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David Harris
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be236d9438
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csr cleanup
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2023-01-13 21:00:06 -08:00 |
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David Harris
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50415a0a12
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csr cleanup
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2023-01-13 20:55:21 -08:00 |
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David Harris
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25d8566694
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csr comments
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2023-01-13 20:49:34 -08:00 |
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David Harris
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543d9d379b
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trap comments
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2023-01-13 19:50:44 -08:00 |
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David Harris
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b613722617
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trap comments
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2023-01-13 19:44:38 -08:00 |
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David Harris
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74d3e0aa40
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privileged comments
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2023-01-13 17:57:38 -08:00 |
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Ross Thompson
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76a9e7d963
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Merge branch 'rastemp'
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2023-01-13 18:09:50 -06:00 |
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Ross Thompson
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0e215ac3c6
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Removed 1 bit from instruction classification.
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2023-01-13 15:19:53 -06:00 |
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David Harris
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fdcb1f08ce
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Privileged unit formatting
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2023-01-12 07:41:30 -08:00 |
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David Harris
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93233fbb45
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Restructured negateintres to avoid lint error, but one still shows on shiftcorrection
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2023-01-12 07:28:52 -08:00 |
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David Harris
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768c1bc703
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Header comments
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2023-01-12 04:35:44 -08:00 |
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David Harris
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8c6ddcc15b
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changed name to CORE-V-WALLY
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2023-01-11 15:15:08 -08:00 |
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David Harris
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3ea4dd4898
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Changed Wally to CORE-V Wally
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2023-01-11 14:03:44 -08:00 |
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David Harris
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739c2c8322
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Changed MIT license to Solderpad License
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2023-01-10 11:35:20 -08:00 |
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David Harris
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dc526c92bd
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Removed unused signals
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2023-01-07 06:06:54 -08:00 |
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Ross Thompson
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78e441fb38
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More branch predictor cleanup.
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2023-01-05 17:19:27 -06:00 |
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Ross Thompson
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0737efc86c
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More branch predictor cleanup.
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2023-01-05 13:36:51 -06:00 |
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Ross Thompson
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0d6ce1d459
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Fixed bug with the performance counters not updating.
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2022-12-24 14:24:17 -06:00 |
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Ross Thompson
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a2de53aeeb
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Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
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2022-12-23 15:10:37 -06:00 |
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David Harris
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0505f1fd37
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Moved InstrValidNotFLushed to csr including InstrValidM
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2022-12-23 00:27:44 -08:00 |
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David Harris
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3b1fe78bdc
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Removed unused StallW from CSRs
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2022-12-23 00:21:36 -08:00 |
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David Harris
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0a7ed944a5
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Revert to 98b824
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2022-12-22 23:58:14 -08:00 |
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David Harris
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2d72bed1f4
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Removed unused signals in FPU and CSR
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2022-12-22 22:59:05 -08:00 |
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David Harris
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d4bedca1bf
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Code cleanup
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2022-12-22 10:04:50 -08:00 |
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David Harris
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6d46261350
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comment cleanup
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2022-12-21 12:39:09 -08:00 |
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David Harris
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c7f3aae084
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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c3b43b2fac
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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0b4186f1e8
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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David Harris
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5d91b3044f
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Clean up vecgtored interrupts
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2022-12-20 16:53:09 -08:00 |
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David Harris
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dd0a02f0c8
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Converted tvecmux to structural
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2022-12-20 16:24:04 -08:00 |
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Ross Thompson
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80be2e7be5
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privileged pc mux cleanup.
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2022-12-20 18:05:44 -06:00 |
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Ross Thompson
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97593e8a6f
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Moved privileged pc logic into privileged unit.
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2022-12-20 17:55:45 -06:00 |
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Ross Thompson
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65cbff9283
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Changed long names of vectored pcm signals.
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2022-12-20 17:01:20 -06:00 |
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David Harris
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caf457106a
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Replaced || and && with single ops
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2022-12-20 01:33:35 -08:00 |
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David Harris
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378c40002f
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Clean up interrupt masking by Commit
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2022-12-16 08:27:39 -08:00 |
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Ross Thompson
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1e2180ef98
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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56cc04316c
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Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.
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2022-10-02 16:21:21 -05:00 |
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Ross Thompson
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638e506d0b
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Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
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2022-09-28 17:39:51 -05:00 |
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David Harris
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113258a0d0
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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c7ec9282fe
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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