Xavi/cvw
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1987 Commits

Author SHA1 Message Date
David Harris
1ec42b9d50 sdc cleanup 2023-01-14 16:49:44 -08:00
David Harris
3ad4ae352c uncore cleanup 2023-01-14 06:15:35 -08:00
David Harris
0c91505f41 Wallypipeliendcore/soc cleanup 2023-01-14 05:57:50 -08:00
David Harris
10f76dd7e6 csr & wally cleanup 2023-01-13 22:25:19 -08:00
David Harris
efe7e88258 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
90e7aa2d50 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
9526479782 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
c9c174de49 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
be236d9438 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
50415a0a12 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
25d8566694 csr comments 2023-01-13 20:49:34 -08:00
David Harris
543d9d379b trap comments 2023-01-13 19:50:44 -08:00
David Harris
b613722617 trap comments 2023-01-13 19:44:38 -08:00
David Harris
74d3e0aa40 privileged comments 2023-01-13 17:57:38 -08:00
Ross Thompson
4c78bcade8 Possible improvement to gshare. 2023-01-13 18:50:01 -06:00
Ross Thompson
76a9e7d963 Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
886e4e2935 Partial fix to RAS prediction accurracy. 2023-01-13 18:05:47 -06:00
Ross Thompson
4aa2b5737f Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
0e215ac3c6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
de7f3b14fc More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
55169fa9b0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-13 10:26:07 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860 Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
David Harris
fdcb1f08ce Privileged unit formatting 2023-01-12 07:41:30 -08:00
David Harris
e58879f2d0 restructured code for lint error related to CORRSHIFTSZ 2023-01-12 07:34:37 -08:00
David Harris
93233fbb45 Restructured negateintres to avoid lint error, but one still shows on shiftcorrection 2023-01-12 07:28:52 -08:00
David Harris
1ad6ac1393 MDU comment cleanup 2023-01-12 07:15:14 -08:00
David Harris
768c1bc703 Header comments 2023-01-12 04:35:44 -08:00
Ross Thompson
b96a53df0a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-11 23:02:14 -06:00
Katherine Parry
77a982c977 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
67d474995e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 19:48:37 -08:00
David Harris
bfd47ff7f5 Removed unused wallypipelinedsocwrapper 2023-01-11 19:48:34 -08:00
Ross Thompson
e0867b1840 Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
aba1df9abf Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 18:52:49 -06:00
Ross Thompson
318ceba34d Improved LSU formating. 2023-01-11 18:52:46 -06:00
sarah-harris
796a189451 privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
Ross Thompson
ad22a9ea02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:26:11 -06:00
sarah-harris
203cc164d9 Added Sarah.Harris@unlv.edu to alu.sv 
Added Sarah.Harris@unlv.edu to alu.sv
 2023-01-11 15:20:41 -08:00
Ross Thompson
b60e9730a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
9a057ef5cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
a8931e0211 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:09:23 -06:00
Katherine Parry
4556839960 fixed typo bug in fpu 2023-01-11 17:07:02 -06:00
Ross Thompson
6999b4562e Updated branch predictor. 2023-01-11 17:00:45 -06:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
99ff78b902 FPU cleanup 2023-01-11 12:27:00 -08:00
David Harris
4ff2627a50 fpu cleanup 2023-01-11 12:18:06 -08:00
David Harris
d1bfdddd8c Rename FP and FPU to F in signal names 2023-01-11 11:46:36 -08:00
David Harris
15026f61f7 FPU comments 2023-01-11 11:31:28 -08:00
David Harris
654abcde61 Replaced MDUE with IntDivE in FDIVSQRT 2023-01-11 11:06:37 -08:00
Ross Thompson
1df9c5f13e Optimized gshare. 2023-01-10 18:12:48 -06:00
David Harris
f6987fab8c Switched to XZeroE from NumerZeroE in square root preprocessor 2023-01-10 12:37:49 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
446b5fa83f Division constant cleanup 2023-01-10 11:14:59 -08:00
David Harris
4a34007b49 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-09 13:04:37 -08:00
David Harris
b2ec52c94d Changed DIVN from NF+3 to NF+2, cleanup 2023-01-09 13:04:34 -08:00
Ross Thompson
f330d877ac Added folded gshare predictor with k=16 and depth=10. 2023-01-09 14:41:03 -06:00
David Harris
48f31d4b24 Divider constant cleanup, made CORRSHIFTSZ consistent 2023-01-09 12:34:19 -08:00
Ross Thompson
302a2e0116 Added better branch predictor to fpga config. 2023-01-09 13:46:30 -06:00
Ross Thompson
ca55bd8444 Fixed branch predictor. 2023-01-09 13:45:49 -06:00
Ross Thompson
6a616617d1 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
816006ac1b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-09 00:18:11 -06:00
Ross Thompson
6326e6984c Might have actually solved the gshare bug. 2023-01-09 00:11:25 -06:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
David Harris
d7e420e350 Cache code cleanup 2023-01-07 15:49:18 -08:00
David Harris
dc12291ee3 Cache code cleanup 2023-01-07 15:46:23 -08:00
David Harris
057183bcc9 Cache code cleanup 2023-01-07 15:44:44 -08:00
David Harris
0a25f18a07 Cache code cleanup 2023-01-07 15:42:08 -08:00
David Harris
0ad707f1a5 Cache code cleanup 2023-01-07 15:39:13 -08:00
Ross Thompson
bf08c57ab0 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
475becb414 Removed unused rv64BP config. 2023-01-07 12:17:40 -06:00
David Harris
f541a277a8 Remove unused CACHE_ENABLED parameter 2023-01-07 09:57:24 -08:00
David Harris
33c910f952 Remove unused signals 2023-01-07 06:26:29 -08:00
David Harris
dc526c92bd Removed unused signals 2023-01-07 06:06:54 -08:00
David Harris
01525399cc Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
David Harris
21b9f50851 Remove conditional from inside decompress module 2023-01-07 05:51:47 -08:00
David Harris
8506f120e1 Remove unused signals 2023-01-07 05:46:22 -08:00
David Harris
44352ced64 Branch logic simplification and remove unused signals 2023-01-07 05:42:34 -08:00
David Harris
d8f0425467 vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
David Harris
f4cb652a00 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-07 04:49:40 -08:00
David Harris
2188ff879b code cleanup 2023-01-07 04:49:25 -08:00
Ross Thompson
f119b492bb Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
7223d1e05c Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Katherine Parry
1bcb1725f5 renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
David Harris
c260354817 Removed unused UARCH configuration entries 2023-01-06 05:11:14 -08:00
Ross Thompson
01d4e942d0 Added more missing files. 2023-01-06 00:12:08 -06:00
Ross Thompson
8a5916ce66 Addd missing file. 2023-01-06 00:09:18 -06:00
Ross Thompson
09bb733088 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00