Ross Thompson
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1cc258ade1
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Progress towards the test bench flush.
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2021-07-12 14:22:13 -05:00 |
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bbracker
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d3dd70e3e6
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more completely uncomment MMU tests to make sim wally work
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2021-07-06 14:33:52 -04:00 |
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Kip Macsai-Goren
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20cd0e208b
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added new mmu tests to makefrag and commented out in the testbench
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2021-07-05 10:54:30 -04:00 |
|
David Harris
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5f91b339aa
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Added F_SUPPORTED flag to disable floating point unit when not in MISA
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2021-07-05 10:30:46 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ben Bracker
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59b177beac
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stop busybear from hanging
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2021-07-02 17:22:09 -05:00 |
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bbracker
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13cf7c0934
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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5b47da21ba
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made testbench-linux's PCDwrong be FlushD
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2021-06-25 08:15:19 -04:00 |
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Katherine Parry
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7e3483b283
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FPU forwarding reworked pt.1
|
2021-06-24 18:39:18 -04:00 |
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bbracker
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13df69abdb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-24 01:42:41 -04:00 |
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bbracker
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be962cb1ff
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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Katherine Parry
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8eed89616c
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fpu clean-up
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2021-06-23 16:42:40 -04:00 |
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Katherine Parry
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353a27f12f
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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David Harris
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7930c2ebb4
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Commented out 100k tests to improve speed
|
2021-06-21 01:43:18 -04:00 |
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David Harris
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1ec90a5e1f
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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bbracker
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bf3c2dc089
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-20 22:29:40 -04:00 |
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bbracker
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3000c27acd
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linux actually uses FPU now!
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2021-06-20 22:29:21 -04:00 |
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Katherine Parry
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2b67f25683
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all rv64f instructions except convert, divide, square root, and FLD pass
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2021-06-20 20:24:09 -04:00 |
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bbracker
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2643130c41
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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14ae87ff0a
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testbench update b/c QEMU extends 32b CSRs to 64b
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2021-06-20 09:24:19 -04:00 |
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bbracker
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c77aabdc6f
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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918ff5093a
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MSTATUS workaround
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2021-06-20 04:48:09 -04:00 |
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bbracker
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069a79fafd
|
workaround for ignoring MTIME
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2021-06-20 02:26:39 -04:00 |
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bbracker
|
d62d9a7aac
|
make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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bbracker
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8d242d73b5
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fixed PCtext error by using blocking assignments
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2021-06-18 17:37:40 -04:00 |
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bbracker
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03a45aeef1
|
restore graphical buildroot sim
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2021-06-18 11:58:16 -04:00 |
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bbracker
|
faae30c31c
|
remove unused testbench-busybear.sv
|
2021-06-18 08:15:19 -04:00 |
|
David Harris
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35c74348a4
|
allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
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336936cc39
|
Cleaned up name of MTIME register in CSRC
|
2021-06-18 07:53:49 -04:00 |
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bbracker
|
5b96f7fbd7
|
making linux waveforms more useful
|
2021-06-17 08:37:37 -04:00 |
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bbracker
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b459d0cc80
|
changed parsedCSRs2] to parsedCSRs
|
2021-06-17 05:18:14 -04:00 |
|
David Harris
|
01d6ca1e2a
|
Fixed lint WIDTH errors
|
2021-06-09 20:58:20 -04:00 |
|
David Harris
|
b613f46c2d
|
Resized BOOT TIM to 1 KB
|
2021-06-08 14:04:32 -04:00 |
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bbracker
|
cc91c774a6
|
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
|
2021-06-08 12:41:25 -04:00 |
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bbracker
|
e7e4105931
|
* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
|
2021-06-08 12:32:46 -04:00 |
|
Kip Macsai-Goren
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c96695b1b6
|
implemented simpler page mixers, cleaned up a bit
|
2021-06-07 18:32:34 -04:00 |
|
David Harris
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2ae5ca19b5
|
Continued merge
|
2021-06-07 12:49:47 -04:00 |
|
David Harris
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ff62000e2c
|
Second attept to commit refactoring config files
|
2021-06-07 12:37:46 -04:00 |
|
David Harris
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dc0b19dfaa
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
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d5ec797ba4
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|
Katherine Parry
|
75a6097467
|
fixed lint warnings for fpu and lzd
|
2021-06-05 12:06:33 -04:00 |
|
Kip Macsai-Goren
|
22e8e06ac7
|
moved privilege dfinitions into wally-constants, upgraded relevant includes
|
2021-06-04 17:55:07 -04:00 |
|
Katherine Parry
|
fc65aedbd6
|
Double-precision FMA instructions
|
2021-06-04 14:00:11 -04:00 |
|
Kip Macsai-Goren
|
1ea9b94cf1
|
added tests for SV48 and translation off with vmem
|
2021-06-03 14:28:52 -04:00 |
|
James E. Stine
|
2eeb12c674
|
Updates to muldiv.sv for 32-bit div/rem
|
2021-06-01 15:31:07 -04:00 |
|
Ross Thompson
|
89ad4477e4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-06-01 11:33:12 -05:00 |
|
Ross Thompson
|
857f59ab5c
|
Now have global history working correctly.
|
2021-06-01 10:57:43 -05:00 |
|
James E. Stine
|
ddbdd0d5a2
|
Modify muldiv.sv to handle W instructions for 64-bits
|
2021-05-31 23:27:42 -04:00 |
|
bbracker
|
39ae743543
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
|
2021-05-28 23:11:37 -04:00 |
|
Katherine Parry
|
778ba6bbf5
|
classify unit created and passes imperas tests
|
2021-05-27 18:53:55 -04:00 |
|