David Harris
7826cf0bcb
Cleaned up otfc4
2022-09-19 00:58:20 -07:00
David Harris
6bab8f0e3f
OTFC simplification
2022-09-19 00:51:56 -07:00
David Harris
362056f53d
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
David Harris
32028c437c
fdiv cleanup
2022-09-19 00:32:34 -07:00
David Harris
b7b082482f
Division working again for radix 2 with unified OTFC
2022-09-19 00:30:30 -07:00
David Harris
91194a9c3e
Unified on-the-fly conversion working for radix 2; broke radix-4 division
2022-09-19 00:04:00 -07:00
David Harris
9fb3382ec3
Added 2 bits to C to initialize properly
2022-09-18 22:44:22 -07:00
David Harris
33933dd6b0
Added 2 bits to C to initialize properly
2022-09-18 22:42:35 -07:00
David Harris
24aa410984
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-18 21:27:36 -07:00
David Harris
198a134304
FP testbench
2022-09-18 21:27:21 -07:00
David Harris
1187187a5c
Divide testfloat starts with half-precision tests
2022-09-18 06:46:47 -07:00
Ross Thompson
6250a65ede
added new constraints for fpga.
2022-09-17 22:20:06 -05:00
Ross Thompson
0fb45cffa1
Removed NonIROM and NonDTIM select signals from IFU and LSU.
2022-09-17 22:01:03 -05:00
Ross Thompson
cc1ba84637
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Kip Macsai-Goren
3f4c825a1a
added mstatus uxl, sxl bit tests (not tested in regression yet)
2022-09-18 00:11:29 +00:00
Kip Macsai-Goren
dda3b2d383
ported endianness tests to 32 bits (not tested in regression yet)
2022-09-18 00:10:29 +00:00
Kip Macsai-Goren
99596fac84
Fixed typos in existing endianness test
2022-09-18 00:09:52 +00:00
Kip Macsai-Goren
657e19df08
added full coverage of subword loads and stores to endianness test
2022-09-17 23:14:38 +00:00
David Harris
f65d941561
Reduced number of cycles required for lower-precision sqrt
2022-09-17 09:55:34 -07:00
David Harris
54ad15d595
Starting to adust number of cycles for division/sqrt
2022-09-17 05:58:59 -07:00
cturek
f07d4b3481
Fixed j1 to align with new C reg
2022-09-16 02:15:48 +00:00
Kip Macsai-Goren
a4fc5d3476
Created initial endianness tests
2022-09-16 01:06:26 +00:00
David Harris
a7b5a0419a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-15 12:49:21 -07:00
David Harris
aa1f3ca2be
renamed endianswap
2022-09-15 12:49:18 -07:00
Ross Thompson
4c8ae8b421
Fixed subword read to work with bigendian.
2022-09-15 14:08:04 -05:00
David Harris
877cc63063
FDIVSQRT cleanup
2022-09-15 09:10:57 -07:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
a536829824
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 13:59:22 -05:00
cturek
5b35473339
Added shift for radix 4 sqrt
2022-09-14 17:34:24 +00:00
cturek
9757d8ce3e
Moved X-1 to preproc
2022-09-14 17:26:56 +00:00
cturek
0f5b38a6f0
Delete srt
2022-09-14 17:02:42 +00:00
cturek
8378d6b871
removed unnecessary XZero from wsmux
2022-09-14 16:59:52 +00:00
David Harris
4038c4faa9
ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-14 09:42:17 -07:00
Ross Thompson
2ae62c2869
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
2babf1fd7a
Removed unused signals
2022-09-12 11:35:35 -07:00
David Harris
f45bb25618
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 16:05:58 -07:00
David Harris
1688d544b9
Moved C to shift before rather than after using in an iteration
2022-09-08 16:05:53 -07:00
David Harris
1c3064af08
divsqrt comment cleanup
2022-09-08 15:40:42 -07:00
Ross Thompson
33ef158ff4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 17:15:46 -05:00
David Harris
e0a9b19008
CSA-based completion detection
2022-09-08 14:58:08 -07:00
Ross Thompson
f5e8021707
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 15:55:30 -05:00
Ross Thompson
8618045bf2
Optimization. Able to remove hptw address muxes from the E stage.
2022-09-08 15:51:18 -05:00
David Harris
6b21a9c4c7
ZMerge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-08 11:38:08 -07:00
David Harris
22455f7743
embench cleaned up
2022-09-08 11:38:01 -07:00
Ross Thompson
d12ceb46b0
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
Ross Thompson
fbea27bd69
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 16:36:51 -05:00
Ross Thompson
ae4a55471d
Oups fixed order of ending swap with mux between cache and fetch buffer.
2022-09-07 16:29:47 -05:00
David Harris
f628622ea0
Factored out aplusbeq0 unit
2022-09-07 11:36:35 -07:00
David Harris
c2f81e309b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
