Ross Thompson
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1aabee0478
|
Updated the config so the tim has a bigger range.
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2021-07-16 12:35:00 -05:00 |
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Ross Thompson
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b3bf04d474
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Updated wave file.
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2021-07-16 12:34:37 -05:00 |
|
Ross Thompson
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46bce70e42
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Fixed walker fault interaction with dcache.
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2021-07-16 12:22:13 -05:00 |
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Ross Thompson
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e0f719d513
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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Kip Macsai-Goren
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abd5b1c02d
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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Ross Thompson
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e5d624c1fa
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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fa26aec588
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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fd1de6b047
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Updated wave file.
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2021-07-15 11:04:49 -05:00 |
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Ross Thompson
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b9902b0560
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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8610ef204c
|
Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
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2021-07-15 10:16:16 -05:00 |
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Ross Thompson
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704f4f724e
|
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
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2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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ba1e1ec231
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Katherine Parry
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c74d26eea4
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Ross Thompson
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c79650b508
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Added d cache StallW checks for any time the cache wants to go to STATE_READY.
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2021-07-14 17:25:50 -05:00 |
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Ross Thompson
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2c946a282f
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Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
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Katherine Parry
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f5bfdf46db
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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Ross Thompson
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e91501985c
|
Routed CommittedM and PendingInterruptM through the lsu arb.
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2021-07-14 16:18:09 -05:00 |
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Ross Thompson
|
adce800041
|
Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
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2021-07-14 15:47:38 -05:00 |
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Ross Thompson
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d78e31e9df
|
Forgot to include one hot decoder.
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2021-07-14 15:46:52 -05:00 |
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Ross Thompson
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f4295ff097
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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bbracker
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335afb14e7
|
testvector unlinker for dev purposes
|
2021-07-14 11:05:34 -04:00 |
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James Stine
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e6d19be87c
|
put back for now to test fdiv
|
2021-07-14 06:48:29 -05:00 |
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bbracker
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46e704b7ef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-14 00:21:39 -04:00 |
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bbracker
|
92899b33f8
|
make testvector scripts agree with new file structure; use symbols to determine end of linux boot
|
2021-07-14 00:21:29 -04:00 |
|
Ross Thompson
|
9b756d6a94
|
Implemented uncached reads.
|
2021-07-13 23:03:09 -05:00 |
|
Ross Thompson
|
e8bf502bc2
|
Added CommitedM to data cache output.
|
2021-07-13 22:43:42 -05:00 |
|
bbracker
|
28887bb3d5
|
needed to create a directory for gdb script
|
2021-07-13 19:39:57 -04:00 |
|
Ross Thompson
|
3e57c899a2
|
Partially working changes to support uncached memory access. Not sure what CommitedM is.
|
2021-07-13 17:24:59 -05:00 |
|
James E. Stine
|
46001fef27
|
mod 2 of fpdivsqrt update
|
2021-07-13 16:59:17 -04:00 |
|
James E. Stine
|
8382a17969
|
Update fpdivsqrt item until move into uarch
|
2021-07-13 16:53:20 -04:00 |
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bbracker
|
f2bf4920d7
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 16:16:04 -04:00 |
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bbracker
|
64d22753b5
|
changed QEMU to use different ports
|
2021-07-13 16:15:51 -04:00 |
|
Ross Thompson
|
baa2b5d15f
|
Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
|
2021-07-13 14:51:42 -05:00 |
|
Ross Thompson
|
3c1a717399
|
Fixed the fetch buffer accidental overwrite on eviction.
|
2021-07-13 14:21:29 -05:00 |
|
Ross Thompson
|
32f27cfecf
|
Dcache AHB address generation was wrong. Needed to zero the offset.
|
2021-07-13 14:19:04 -05:00 |
|
Ross Thompson
|
afc1bc9c38
|
Moved StoreStall into the hazard unit instead of in the d cache.
|
2021-07-13 13:20:50 -05:00 |
|
David Harris
|
9de97c1e20
|
Fixed busybear by restoring InstrValidW needed by testbench
|
2021-07-13 14:17:36 -04:00 |
|
Ross Thompson
|
47e16f5629
|
Fixed back to back store issue.
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
|
2021-07-13 12:46:20 -05:00 |
|
David Harris
|
2ba82d1a5c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-13 13:26:51 -04:00 |
|
David Harris
|
223086ac33
|
added or.sv
|
2021-07-13 13:26:40 -04:00 |
|
Katherine Parry
|
ca19b2e215
|
Fixed writting MStatus FS bits
|
2021-07-13 13:22:04 -04:00 |
|
Katherine Parry
|
efdec72df1
|
Fixed writting MStatus FS bits
|
2021-07-13 13:20:30 -04:00 |
|
David Harris
|
93d6688c3c
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-13 13:19:24 -04:00 |
|
David Harris
|
b5dddec858
|
Fixed InstrValid from W to M stage for CSR performance counters
|
2021-07-13 13:19:13 -04:00 |
|
bbracker
|
3565580f40
|
updated buildroot make procedure to incorporate configs more robustly
|
2021-07-13 12:40:14 -04:00 |
|
Ross Thompson
|
224e3b2991
|
Fixed subword write. subword read should not feed into subword write.
|
2021-07-13 11:21:44 -05:00 |
|
Ross Thompson
|
30b7c4436c
|
restored rv64ic config back to full sized dtim.
|
2021-07-13 11:18:54 -05:00 |
|
Ross Thompson
|
3951eb56f5
|
Modularized the shadow memory to reduce performance hit.
|
2021-07-13 10:55:57 -05:00 |
|
Ross Thompson
|
e594eb540d
|
Got the shadow ram cache flush working.
|
2021-07-13 10:03:47 -05:00 |
|
bbracker
|
99587f58f7
|
whoops I accidentally made main.config into a symbolic link; now it is a source file
|
2021-07-13 11:00:01 -04:00 |
|