129 Commits

Author	SHA1	Message	Date
David Harris	42275e92ed	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
bbracker	850a2e9329	added a delay to sel signals	2021-03-05 15:07:34 -05:00
bbracker	77e2e357a7	more merging fixes	2021-03-05 14:36:07 -05:00
bbracker	ed4ff1ecd0	remove deprecated mem signals	2021-03-05 14:27:38 -05:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	dfae278ffb	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	735c6789ea	busybear: comment out instraccessfaultf for imem for now	2021-03-04 20:26:41 +00:00
Noah Boorstin	827dfd774b	Merge branch 'main' into busybear ... Conflicts: wally-pipelined/src/uncore/imem.sv	2021-03-04 20:16:03 +00:00
Teo Ene	f060f6cb9d	Fix to 32-bit option of commit babe6ce9db	2021-03-04 01:33:34 -06:00
Noah Boorstin	62b441f3f5	busybear: probably discovered bug in ahb code	2021-03-01 20:56:04 +00:00
Noah Boorstin	4833b36535	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	26d4024b33	busybear: fix bootram range	2021-03-01 17:45:21 +00:00
Teo Ene	babe6ce9db	Properly implemented the fix from commit 31c07b2adc	2021-02-28 22:22:04 -06:00
Noah Boorstin	f306d2d2e1	busybear: start preloading bootmem	2021-02-28 20:43:57 +00:00
Noah Boorstin	6e70ae8b3d	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
Noah Boorstin	edd5e9106d	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	24f767a404	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
Teo Ene	6be5bb1f84	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	31c07b2adc	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
bbracker	9231646fb3	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	aee44bb343	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00