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310 Commits

Author SHA1 Message Date
Ross Thompson
cc48cdc97b Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
Ross Thompson
a9a7054e2f Merge branch 'main' of https://github.com/openhwgroup/cvw 
This merges the branch predictor improvements into the main repo.
 2023-01-29 15:24:20 -06:00
Ross Thompson
f93eaeef8e Fixed another bug with the speculative gshare with instruction class prediction. 2023-01-29 00:33:40 -06:00
Ross Thompson
6371d91b37 Added another performance counter to track overall branch miss-predictions. 2023-01-28 17:50:46 -06:00
Ross Thompson
8a277f6b75 Possible fix for speculative gshare. 2023-01-28 16:14:19 -06:00
Ross Thompson
a212960352 Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. 2023-01-27 11:34:45 -06:00
David Harris
237e3a620f Removed suggestion about make allclean 2023-01-27 05:57:05 -08:00
Ross Thompson
4fa2dcc2a5 Changed the performance counters to track different data. 
Now rather than tracking jump(r) we track jump(r) and taken branches.
 2023-01-26 13:21:28 -06:00
Ross Thompson
3dc441ff8c Intermediate commit. Passes regression tests, but RAS is not correct. 2023-01-25 19:39:18 -06:00
Ross Thompson
5da1aeeef1 Improved RAS again. 2023-01-25 17:10:52 -06:00
David Harris
45218863af test 2023-01-20 15:23:38 -08:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
aa942feedc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
c73bea83cd Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
caff6e788c Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
sarah-harris
4e9a7a6403 Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
David Harris
f93b7cfda7 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
12e12e464a Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
Ross Thompson
78e441fb38 More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
9d03109f34 Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
0eceeeeeaa Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
David Harris
fb0b2d4227 Moved floating-point tests earlier in Wally config 2022-12-25 22:31:20 -08:00
Ross Thompson
6e9d1eb180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-23 19:51:23 -06:00
Katherine Parry
4b50ffac91 reworked negitive sticky bit handeling in fma 2022-12-23 17:01:34 -06:00
Ross Thompson
a2de53aeeb Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
David Harris
9e21358d75 Removed unused signals from FPU 2022-12-23 00:18:39 -08:00
David Harris
56312cd0a6 Clean up unused FPU signals 2022-12-22 23:53:09 -08:00
Ross Thompson
2cc4d66ded Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
206bc7daa6 Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
b1475df5e1 Wavefile updates. 2022-12-22 19:45:02 -06:00
Ross Thompson
a02b40cf02 Changes to wave file. 2022-12-21 08:41:47 -06:00
David Harris
dd0a02f0c8 Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
David Harris
e7702e48b7 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
4f56e6ff5d I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl. 2022-12-18 18:30:35 -06:00
Ross Thompson
ebdac1a9d0 Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
Ross Thompson
73fd3fe040 Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6 At long last found the subtle bug in the LRU. 
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
 2022-12-17 10:03:08 -06:00
Ross Thompson
731fbfc851 Oups found a bug with the new flush cache states. 2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896 Cleanup of cache flush fsm enhancement. 2022-12-16 15:36:53 -06:00
Ross Thompson
e425ecac96 Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
David Harris
4365c99b52 Refactored stalls and flushes, including FDIV flush with FlushE 2022-12-15 10:56:18 -08:00
David Harris
5b040b7935 Regression delete wkdir files to prevent spurious failures 2022-12-15 10:24:58 -08:00
David Harris
f64c0589fe FPU test list 2022-12-01 10:18:36 -08:00
Ross Thompson
f9ffcf377b Reverted the IROM/DTIM address range modelsim assignment. 2022-11-30 17:13:33 -06:00
Ross Thompson
bfd238a4fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-11-30 13:30:37 -06:00
Ross Thompson
8692ccbafb Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00