cvw/pipelined/regression
2022-12-22 19:45:02 -06:00
..
slack-notifier
wave-dos
buildrootBugFinder.py
fpga-wave.do
lint-wally Converted tvecmux to structural 2022-12-20 16:24:04 -08:00
linux-wave.do Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back. 2022-12-17 23:47:49 -06:00
make-tests.sh
Makefile
makefile-memfile
regression-wally Fixed regression-wally to correct remove and mkdir wkdir. 2022-12-16 12:51:21 -06:00
sim-buildroot
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
testfloat.do
wally-harvard.do
wally-pipelined-batch.do
wally-pipelined.do Updated tests for fpga and BP. 2022-12-18 16:24:26 -06:00
wave-all.do
wave-fpu.do
wave.do Wavefile updates. 2022-12-22 19:45:02 -06:00