Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,426 Commits 14 Branches 1 Tag 31 MiB
0e023e29d8
Commit Graph

2426 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
c1d6550ccb Removed generate statements 2022-01-05 14:35:25 +00:00
Ross Thompson
f89c1d91dc Renamed most signals inside cache.sv so they are agnostic to i or d. 2022-01-04 23:52:42 -06:00
Ross Thompson
9eda7c12bd the i and d caches now share common verilog. 2022-01-04 23:40:37 -06:00
Ross Thompson
b06c3b8acd parameterized the caches with the goal of using common rtl for both i and d caches. 2022-01-04 22:40:51 -06:00
Ross Thompson
06168e67e4 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
Ross Thompson
d94a1c6404 Fixed bug where last line of dcache was not written back to memory on dcache flush. 2022-01-04 21:55:48 -06:00
Ross Thompson
0dd61a57da Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-04 18:41:52 -06:00
Ross Thompson
3c3c6d0fe8 Fixed dcache flush. 2022-01-04 18:40:58 -06:00
David Harris
08e6a10480 Removed imperas mmu tests; using wallypriv instead 2022-01-04 23:14:53 +00:00
Kip Macsai-Goren
17b9143d10 cleaned up Imperas tests to pass make 2022-01-04 21:32:21 +00:00
Kip Macsai-Goren
87ba45ce36 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 21:30:51 +00:00
Kip Macsai-Goren
0ee4e03cd6 fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh. 2022-01-04 21:30:38 +00:00
David Harris
57daff45c8 Fixed bad address for F/fmsub_b18-01 2022-01-04 21:04:06 +00:00
Kip Macsai-Goren
ad3ee6bc08 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 20:58:08 +00:00
David Harris
1f07470477 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 19:47:51 +00:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Kip Macsai-Goren
d1709e98d2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 18:16:46 +00:00
Ross Thompson
f3a300738f Added mmu tests to regression-wally. 
imperas64mmu passes but imperas32mmu does not.
 2022-01-04 11:13:36 -06:00
Ross Thompson
7ac412eb8e Modified dcache to ensure nontranslated index is used. 2022-01-04 10:53:53 -06:00
Kip Macsai-Goren
9ad44e3e97 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 06:38:28 +00:00
Ross Thompson
1ea267cab5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-03 23:49:28 -06:00
Ross Thompson
08b439b9e9 Fixed icache stalling cpu when doing an uncached operation. 2022-01-03 23:49:19 -06:00
Kip Macsai-Goren
cc0409b9d6 update 64 bit tests to make make work correctly and general cleanup 2022-01-04 05:02:33 +00:00
Kip Macsai-Goren
cbe255230e Update 32 bit memory tests to make make work correcttly and generally cleanup 2022-01-04 04:59:47 +00:00
Kip Macsai-Goren
a74b0b8f56 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 04:55:36 +00:00
Ross Thompson
4b4aa11684 Reordered inputs/outputs in caches. 2022-01-03 22:52:50 -06:00
Ross Thompson
fa39de9cef Added generate around the spill logic so it is only used if supporting compressed instructions. 2022-01-03 22:23:04 -06:00
Ross Thompson
36451bbd15 Minor improvement to icache. 2022-01-03 22:00:35 -06:00
Ross Thompson
a130c03478 More Icache clean up. 2022-01-03 21:22:34 -06:00
Ross Thompson
c2a9b3bc79 Major icache cleanup. 2022-01-03 21:12:17 -06:00
Ross Thompson
5a438a9498 Removed spill support from icache. 2022-01-03 21:03:02 -06:00
Ross Thompson
697717707f The ifu now directly supports compressed without the icache providing the implemenation. 
The icache still constains all the orignal muxing logic to handle spills.  This should be removed.
 2022-01-03 20:49:47 -06:00
Ross Thompson
b7b9e3bd55 Almost working compressed instructions with compressed detection and processing in ifu rather than icache. 2022-01-03 18:10:15 -06:00
Ross Thompson
3adc0d43e7 Prepared the ifu and icache for moving spills to ifu. 2022-01-03 17:09:36 -06:00
Ross Thompson
35c5b9ad50 Fixed bug with the icache. 2022-01-03 15:55:19 -06:00
Ross Thompson
e0c310fea7 Fixed a bug where the instruction fetch got out of sync with the icache. 2022-01-03 13:27:15 -06:00
David Harris
d909e8f371 Replaced && and || with & and | in non-fp files per new style guidelines 2022-01-02 21:47:21 +00:00
David Harris
9693110857 Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
Katherine Parry
9d4e1671c9 some errors in FP ArchTests fixed 2022-01-01 23:50:23 +00:00
David Harris
8d6c48cfb1 Removed .* from MMU. 2021-12-31 07:19:51 +00:00
David Harris
41052178ce Removed .* from CSRs 2021-12-31 07:11:03 +00:00
David Harris
470bb6ed4d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-31 06:40:25 +00:00
David Harris
9f24b4c969 Simplified performance counters 2021-12-31 06:40:21 +00:00
Ross Thompson
b146c71b14 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 18:10:36 -06:00
Ross Thompson
b6fbc4a1e3 Added mux to select between uncache instruction requests and cached instructions requests. 
Cacheless design almost works with the exception of compressed instructions.
 2021-12-30 18:09:37 -06:00
Ross Thompson
58ef91c94b Fixed wave.do. 2021-12-30 17:57:07 -06:00
Ross Thompson
5904bc68c7 Patched up the linux-wave.do file. 2021-12-30 17:53:43 -06:00
David Harris
42df98bc6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 23:40:02 +00:00
David Harris
b96439dd73 Fixes to counters; buildroot still broken 2021-12-30 23:39:59 +00:00
Ross Thompson
8e4467654a Working without dcache. 2021-12-30 16:01:31 -06:00