Xavi/cvw

Configurable RISC-V Processor

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David Harris b36ace221e Renamed wally-pipelined to pipelined		2022-01-04 19:47:41 +00:00
addins	Started adding asynchronous TIMECLK for CLINT	2022-01-02 21:18:16 +00:00
benchmarks/riscv-coremark	Added file showing how to compile riscv toolchain for different extension combinations.	2021-12-19 20:31:55 -06:00
bin	Fixed exe2memfile.pl bug	2021-12-27 00:44:18 +00:00
examples	Added performance counting to sumtest and added imperas32/64periph to testbench.	2021-12-29 00:28:51 +00:00
fpga	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
pipelined	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
tests	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
.gitattributes	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
.gitignore	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
.gitmodules	.gitmodule added dirty riscv-arch-test	2021-12-29 23:50:17 +00:00
LICENSE	Initial Checkin	2021-01-14 23:37:51 -05:00
Makefile	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
README.md	changed readme to reflect submodule updates	2021-11-30 18:26:49 -08:00
setup.sh	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wallyVirtIO.patch	added wallyVirtIO.patch from Ross	2021-12-22 07:04:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

To use Wally on Linux:

git clone https://github.com/davidharrishmc/riscv-wally --recurse-submodules
cd riscv-wally
cd addins
cd riscv-isa-sim
*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated
cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D
<edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
mkdir build
cd build
set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)
../configure --prefix=$RISCV
make (this will take a while to build SPIKE)
sudo make install
cd ../../riscv-arch-test
cp ../riscv-isa-sim/arch_test_target/spike/Makefile.include .
edit Makefile.include
  change line with TARGETDIR to /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target (or whatever your path is) 
  add line export RISCV_PREFIX = riscv64-unknown-elf-  # this might not be needed if you have 32-bit versions of the riscv gcc compiler built separately
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
cd ../../tests
cd imperas-riscv-tests
make
cd ../wally-riscv-arch-test
make
make XLEN=32
exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
cd ../linux-testgen/linux-testvectors
./tvLinker.sh

Notes: Eventually download imperas-riscv-tests separately Move our custom tests to another directory Eventually replace exe2memfile.pl with objcopy