David Harris
|
b4cb9a678a
|
renamed srt to fdivsqrt
|
2022-08-29 04:04:05 -07:00 |
|
David Harris
|
921a49921b
|
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
|
2022-08-26 21:05:20 -07:00 |
|
David Harris
|
6409548c8b
|
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
|
2022-08-26 20:26:12 -07:00 |
|
David Harris
|
906f6f2990
|
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
|
2022-08-26 20:12:03 -07:00 |
|
Ross Thompson
|
109bcd470e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-08-25 16:01:02 -05:00 |
|
David Harris
|
6222e15946
|
Extended HADDR to PA_BITS
|
2022-08-25 13:11:36 -07:00 |
|
Ross Thompson
|
32f86b1b6b
|
Still not working with rv32ic.
|
2022-08-25 15:03:54 -05:00 |
|
Ross Thompson
|
4ad7ccc7f7
|
Possible fixes for earily messup of rv32ic and rv64ic configs.
|
2022-08-25 14:42:08 -05:00 |
|
Ross Thompson
|
bd9401179d
|
BROKEN. Don't use this commit.
Issue running cacheless with bus.
|
2022-08-25 11:02:46 -05:00 |
|
Ross Thompson
|
5cc4f1f1cd
|
Added generate around uncore.
|
2022-08-25 10:35:24 -05:00 |
|
David Harris
|
fe3147806d
|
removed simpleram and modified dtim to use bram1p1rw
|
2022-08-25 03:39:57 -07:00 |
|
David Harris
|
b3a13a01f8
|
Stripped write capaibilty out of rom_ahb
|
2022-08-24 17:23:08 -07:00 |
|
Ross Thompson
|
b650d7e05a
|
Renamed RAM to UNCORE_RAM.
|
2022-08-24 18:09:07 -05:00 |
|
Ross Thompson
|
c636387613
|
Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
|
2022-08-24 17:52:25 -05:00 |
|
Ross Thompson
|
07b2858890
|
added SD card and external ram to common testbench.
|
2022-08-24 13:27:18 -05:00 |
|
Ross Thompson
|
c6927d2ace
|
Modified the lsu/ifu memory configurations.
|
2022-08-24 12:35:15 -05:00 |
|
David Harris
|
9e3d13ca52
|
Q depends on D
|
2022-08-23 08:29:59 -07:00 |
|
David Harris
|
7c91ed38a3
|
LSU minor edits
|
2022-08-23 07:35:47 -07:00 |
|
David Harris
|
b795cf4731
|
Updated testbench assertions.
|
2022-08-23 07:23:24 -07:00 |
|
Ross Thompson
|
21526957cf
|
Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
|
2022-08-21 15:59:54 -05:00 |
|
Ross Thompson
|
dad6770fc3
|
Updated fpga testbench.
|
2022-08-21 14:07:26 -05:00 |
|
Katherine Parry
|
0f077012c3
|
sqrt tests in regression uncommented and pass
|
2022-08-07 23:38:10 +00:00 |
|
Katherine Parry
|
8eeca3319c
|
radix-2 1 copy passes testfloat
|
2022-08-06 22:54:05 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3b970d3ff
|
Partitioned fma into separate files
|
2022-08-01 18:07:38 +00:00 |
|
David Harris
|
da275e3c26
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
David Harris
|
ae4ea00ff0
|
fixed testbench merge comflict
|
2022-07-26 06:21:46 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
094aacdf6f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-25 23:29:08 +00:00 |
|
David Harris
|
ccf8ccfa24
|
Added rv32f tests to RV64gc
|
2022-07-25 23:29:05 +00:00 |
|
David Harris
|
539174f6f6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
Ross Thompson
|
70032bf8f4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-23 08:41:59 -05:00 |
|
Katherine Parry
|
ee7932c804
|
divider sizes reworked to match book
|
2022-07-22 22:02:04 +00:00 |
|
Daniel Torres
|
d95b266d49
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
2bbfd67082
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
44c30ec082
|
fixed error in tests.vh
|
2022-07-22 14:55:55 -07:00 |
|
slmnemo
|
170601af0b
|
Added UART test to peripheral test
|
2022-07-22 14:55:34 -07:00 |
|
Daniel Torres
|
fbe3a1af12
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 13:52:19 -07:00 |
|
Daniel Torres
|
261b9aa5a1
|
commented out embench test that should be commented out
|
2022-07-22 13:52:13 -07:00 |
|
slmnemo
|
0d98ff74b4
|
Added PLIC test to regression
|
2022-07-22 12:35:37 -07:00 |
|
Daniel Torres
|
5d7171f6f8
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
526f70e772
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
49565f944c
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
bd918d37ba
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
a17361870f
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-21 12:50:04 -07:00 |
|
Daniel Torres
|
6e9b4f4075
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
Katherine Parry
|
270216dd02
|
radix-4 division integrated into srt - not tested
|
2022-07-21 19:38:06 +00:00 |
|
Katherine Parry
|
67c99d3d1a
|
added input enables and improved forwarding
|
2022-07-21 01:20:06 +00:00 |
|
Daniel Torres
|
d33d0d22bd
|
commented out embench 2.0 tests
|
2022-07-19 13:36:18 -07:00 |
|