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Author SHA1 Message Date
Alec Vercruysse
7ba2bfd4b6 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9 fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Liam
2a4bc01944 Update tests.vh 2023-04-18 23:15:47 -07:00
Liam
777028e43b Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
fe51108740 a 2023-04-18 22:09:50 -07:00
Kevin Wan
fed7681695 Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
ea39b53c97
Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Cedar Turek
30bd1e2a33 created fdivsqrtcycles, moved cycles calculation from FSM to preproc 2023-04-18 16:14:45 -07:00
Kevin Thomas
385564fe4c Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Ross Thompson
d783456746 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Cedar Turek
871d495ca1 gave integer bits to D instead of adding manually everywhere 2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c moved D flop to preproc 2023-04-18 15:14:17 -07:00
Ross Thompson
bb4ebd9b61 More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
David Harris
d5e2fefe2c
Merge pull request #252 from mcook26/main 
Increase of TLB coverage in IFU
 2023-04-18 05:49:18 -07:00
Miles Cook
5cfd0577d1 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
dd7f5310e4 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
00c61fc5b3 Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Sydeny
f0ff1a4447 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
Ross Thompson
96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Sydeny
4748fa0f6b Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-17 13:51:16 -07:00
Ross Thompson
fad0366d26 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
David Harris
bdd5f5e611
Merge pull request #251 from masonadams25/main 
Removed redundent expression to increase coverage
 2023-04-17 12:37:27 -07:00
Ross Thompson
981fcc6f4a
Merge pull request #249 from davidharrishmc/dev 
DV Test Plan, fdivsqrt, merged exclusions
 2023-04-17 14:32:37 -05:00
Mason Adams
4468086e06
Removed redundent expression to increase coverage 2023-04-17 14:13:26 -05:00
David Harris
d327ed494a Started DV Test Plan 2023-04-17 10:18:06 -07:00
David Harris
b00b8ba366 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
0be81fdfc8 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5 OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
David Harris
171fc0ee7f
Merge pull request #248 from dherreravicioso/main 
Added test coverage for reads to HPM counters and coverage exclusions
 2023-04-16 18:18:31 -07:00
Ross Thompson
5da5b76449 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board. 
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
 2023-04-15 11:13:28 -05:00
Sydeny
af51b6f16c trimming comments on fctrl bug fixes 2023-04-15 00:48:32 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3 
Full I$ coverage
 2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116 replace instances of code duplication for i$ exclusions w/commands 2023-04-14 17:10:39 -07:00
Ross Thompson
c9445384d7 Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure. 2023-04-14 18:02:16 -05:00
Ross Thompson
29146ac839
Merge pull request #247 from AlecVercruysse/code_quality 
Code Quality
 2023-04-14 16:46:39 -05:00
Limnanthes Serafini
5952a4b0a3 Final small fix 2023-04-14 14:15:52 -07:00
Limnanthes Serafini
e20f00a520 Merge branch 'code_quality' of https://github.com/AlecVercruysse/cvw into code_quality 2023-04-14 14:14:40 -07:00