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Author SHA1 Message Date
James E. Stine
4503ad4c87 Add simple example based on original C program built by David Harris for OSU who want to see easy way to convert FP numbers 2023-04-12 17:20:11 -05:00
Alec Vercruysse
800f0245f3 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
e2520c8a27 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
James E. Stine
dee4d49e42 Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
44023e7ee7 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
a433b8a1c1
Merge pull request #234 from AlecVercruysse/cachesim 
CacheSim: Logger improvements, performance logging, sim wrapper
 2023-04-12 03:14:03 -07:00
Limnanthes Serafini
e6269b364f Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
3b6e397172 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
978b475269 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
David Harris
28c02a7e6a Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
David Harris
c5e3b5c68d Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
d60e3aaf53 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006 Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Ross Thompson
2f6ed64e26
Merge pull request #232 from stineje/main 
Mod testing for TestFloat
 2023-04-11 23:22:59 -05:00
James Stine
5d1ad53bc7 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
James Stine
f5201da676 Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
11a5b23bb8 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Limnanthes Serafini
3f7f3d6a42 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
Limnanthes Serafini
b6ecd15eff Cleanup + success message added to CacheSim 2023-04-11 19:28:28 -07:00
David Harris
953518bcba Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-11 19:08:09 -07:00
David Harris
32daa34680
Merge pull request #231 from kipmacsaigoren/priv-tests 
Priv tests Updates for SVADU, and SAIL
 2023-04-11 19:07:13 -07:00
Kip Macsai-Goren
9f30414e97 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
7d9ebf56ed renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
cf50d04a21 removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
b839de4451 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
599ebc572e enabled SVADU for rv32/64gc 2023-04-11 17:42:26 -07:00
Kip Macsai-Goren
c179d76542 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00
Kip Macsai-Goren
41ef59ddfe Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
4bf2a7e15b Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
Ross Thompson
1861ca8c86 Fixed more bugs in the ila debug constraints. 2023-04-11 14:32:53 -05:00
Ross Thompson
0a43c43b0a Merge branch 'main' of github.com:ross144/cvw 2023-04-11 14:31:08 -05:00
Ross Thompson
b015e736a0 Updated to help debut Jacob's crossbar woes. 2023-04-11 14:22:42 -05:00
Ross Thompson
c7104bebd3 Fixed sum bugs with arty a7 ila script. 2023-04-11 10:00:06 -05:00
David Harris
4797f6ca5e
Merge pull request #230 from ACWright256/main 
Excluded coverage for misaligned instructions
 2023-04-11 05:21:09 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
Noah Limpert
a7ec77239f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-10 19:01:32 -07:00
Ross Thompson
6123efd5b2 Updates for arty a7. 2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c Finally building ddr3 xilinx ip from script. 2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f Started putting together the arty a7 board package files. 2023-04-10 13:15:55 -05:00
David Harris
baef1249e7 Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic. ImperasDV is happy with these privileged tests now 2023-04-10 07:05:06 -07:00