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Configurable RISC-V Processor
750 Commits 5 Branches 2 Tags 53 MiB
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12b978fec2
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Ross Thompson 12b978fec2 Eliminated extra register and fixed ports to icache. 
Still need to support physical tag check and write in icache memory.
Still need to reduce to 1 port SRAM in icache.
I would like to refactor the icache code.
2021-05-03 12:04:54 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Created special test for driving the instruction spill error. 2021-04-08 15:05:08 -05:00
wally-pipelined Eliminated extra register and fixed ports to icache. 2021-05-03 12:04:54 -05:00
.gitignore Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor