Rose Thompson
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816e54f451
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Revert "Revmoed file from fpga zbbl which should not have been added."
This reverts commit d6944cdaa4.
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2024-10-14 21:29:02 -05:00 |
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Rose Thompson
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d6944cdaa4
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Revmoed file from fpga zbbl which should not have been added.
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2024-10-03 15:03:15 -05:00 |
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Jordan Carlin
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022b98a64b
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Update all iterative makes to use
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2024-09-29 23:14:19 -07:00 |
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Rose Thompson
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8248f2dd66
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Added MAXSDCCLOCK to parameters set by the FPGA makefile.
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2024-09-03 10:55:15 -07:00 |
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Rose Thompson
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4afdb500d7
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Added missing files.
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2024-09-02 14:46:41 -07:00 |
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Rose Thompson
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869860bc55
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Merge branch 'main' of github.com:ross144/cvw
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2024-09-02 14:08:48 -07:00 |
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Rose Thompson
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9471ccd2fc
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Updated Makefiles and source files to build the zsbl according to the config.
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2024-09-02 14:03:47 -07:00 |
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Rose Thompson
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2e55f1cecc
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Well on the way to a fully automated FPGA build process which
correctly sets the clocks and memory locations.
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2024-09-02 11:19:02 -07:00 |
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Jacob Pease
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44ece7cb96
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Added CVW header to spitest files.
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2024-08-27 14:28:49 -05:00 |
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Jacob Pease
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d649473ec8
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Merge branch 'main' of github.com:openhwgroup/cvw
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2024-08-24 21:57:44 -05:00 |
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Jacob Pease
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ad6734eb6d
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Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full.
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2024-08-24 21:36:29 -05:00 |
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Rose Thompson
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8d40a0a092
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Changed names of fpga IP modules to match textbook. Updated boot.h to
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
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2024-08-22 13:56:50 -07:00 |
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Jacob Pease
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43b17b5058
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Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
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2024-08-20 14:40:50 -05:00 |
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Jacob Pease
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9fae5dfc0a
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Added dynamic SDC Clock selector in bootloader code.
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2024-08-20 12:19:49 -05:00 |
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Jordan Carlin
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564ce83e11
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Update linker scripts to avoid hardcoded /opt/riscv
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2024-08-09 20:15:28 -07:00 |
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Jacob Pease
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2dc7e0f76f
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Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
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2024-08-06 17:36:42 -05:00 |
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Jacob Pease
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280b5baa59
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Added header to new bootloader files.
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2024-08-06 17:28:50 -05:00 |
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Jacob Pease
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665396fdb3
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SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree.
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2024-08-06 16:57:57 -05:00 |
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Jacob Pease
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ad9c98c19c
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Added file necessary to split boot.mem into boot.mem and data.mem.
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2024-08-02 15:36:06 -05:00 |
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Jacob Pease
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897f6561cd
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New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently.
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2024-08-02 15:19:52 -05:00 |
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Jacob Pease
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fcd88d6e6f
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Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display.
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2024-08-02 15:14:30 -05:00 |
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Jacob Pease
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38071d8267
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Updated formatting of gpt.c and boot.c.
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2024-07-31 11:12:05 -05:00 |
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Jacob Pease
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ee980e39f3
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Added function to set SPI clock speed.
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2024-07-31 11:00:44 -05:00 |
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Jacob Pease
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c4ae17c679
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Cleaned up code formatting a bit and added ability to set the SD card clock speed.
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2024-07-31 10:59:41 -05:00 |
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Jacob Pease
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a263f836f2
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Added extra UART macros and functions for code readability and the ability to print decimal numbers.
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2024-07-31 10:58:15 -05:00 |
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Jacob Pease
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3975f60299
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Added carriage returns to line feed characters. UART messages print properly now.
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2024-07-25 13:05:57 -05:00 |
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Jacob Pease
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a36e846b02
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Changed formatting and added new UART divsor calculation from OpenSBI.
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2024-07-25 13:04:27 -05:00 |
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Jacob Pease
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336a413f31
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Added ability to split boot.memfile into boot.mem and data.mem.
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2024-07-25 11:19:15 -05:00 |
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Jacob Pease
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d15be492cb
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Masked lower byte when writing to DLL.
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2024-07-24 22:44:27 -05:00 |
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Jacob Pease
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286d80de7e
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Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future
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2024-07-24 22:43:47 -05:00 |
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Jacob Pease
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0107a400d1
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Added uart header to gpt.c.
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2024-07-24 22:43:16 -05:00 |
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Jacob Pease
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dcb2edf888
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Fixed syntax bugs. inline functions are now static and in the spi.h header.
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2024-07-23 17:00:32 -05:00 |
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Jacob Pease
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5f0addd69a
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Initial pass on SPI based bootloader code finished.
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2024-07-23 16:33:49 -05:00 |
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Jacob Pease
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a8b9e7776b
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Added some minor error checking to gpt.c.
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2024-07-23 16:32:52 -05:00 |
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Jacob Pease
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ab00ea5a5c
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Added sd_read64 to help with block reads and crc checking.
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2024-07-23 16:32:29 -05:00 |
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Jacob Pease
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57eeba5c8c
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Progress made on implementing new disk read function.
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2024-07-23 15:47:23 -05:00 |
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Jacob Pease
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9ccb0eb027
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Removed references to card_type.
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2024-07-23 15:46:18 -05:00 |
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Jacob Pease
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bf65cd2817
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Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c
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2024-07-23 14:18:42 -05:00 |
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Jacob Pease
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b05052311f
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Added sd_cmd and utility SPI functions.
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2024-07-22 16:57:04 -05:00 |
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Jacob Pease
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e91d2c8b14
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Corrected the CRC7 code with the right sequence of instructions.
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2024-07-22 01:19:10 -05:00 |
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Jacob Pease
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c7d869bc96
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Added inital spi based sd card code. Working on CRC7 code that works.
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2024-07-20 14:00:43 -05:00 |
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Jacob Pease
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53b2a51c89
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Added tentative spi_send_byte function.
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2024-07-19 12:30:32 -05:00 |
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Jacob Pease
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34e89e842c
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Added initial spi code to fpga/zsbl
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2024-07-19 11:35:12 -05:00 |
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Jacob Pease
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7a417d7a6c
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Added true bootloader to fpga/zsbl directory.
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2024-05-31 15:28:25 -05:00 |
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Rose Thompson
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6097444b5a
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Added missing file for compiling the fpga zero stage bootloader.
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2024-04-11 10:30:56 -05:00 |
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Rose Thompson
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60f96112db
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Moved the zero stage boot loader to the fpga directory.
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2024-03-01 10:23:55 -06:00 |
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