cvw/fpga/zsbl
Rose Thompson 8d40a0a092 Changed names of fpga IP modules to match textbook. Updated boot.h to
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
2024-08-22 13:56:50 -07:00
..
bios.s
boot.c Changed names of fpga IP modules to match textbook. Updated boot.h to 2024-08-22 13:56:50 -07:00
boot.h
fail.c
fail.h
gpt.c
gpt.h
linker1000.x
Makefile
riscv.h
riscv.S
sd.c
sd.h
spi.c
spi.h
splitfile.sh
time.c
time.h
uart.c
uart.h