cvw/fpga/zsbl
Rose Thompson 2e55f1cecc Well on the way to a fully automated FPGA build process which
correctly sets the clocks and memory locations.
2024-09-02 11:19:02 -07:00
..
boot.c Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-24 21:57:44 -05:00
boot.h Well on the way to a fully automated FPGA build process which 2024-09-02 11:19:02 -07:00
fail.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
fail.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
gpt.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
gpt.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
linker1000.x Update linker scripts to avoid hardcoded /opt/riscv 2024-08-09 20:15:28 -07:00
Makefile Well on the way to a fully automated FPGA build process which 2024-09-02 11:19:02 -07:00
riscv.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
riscv.S Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
sd.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
sd.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
spi.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
spi.h New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. 2024-08-02 15:19:52 -05:00
splitfile.sh Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv 2024-08-06 17:36:42 -05:00
time.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
time.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
uart.c Added header to new bootloader files. 2024-08-06 17:28:50 -05:00
uart.h Added header to new bootloader files. 2024-08-06 17:28:50 -05:00