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Added MAXSDCCLOCK to parameters set by the FPGA makefile.

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This commit is contained in:
Rose Thompson 2024-09-03 10:55:15 -07:00
parent d0ae6bf217
commit 8248f2dd66
4 changed files with 12 additions and 11 deletions
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3
fpga/generator/Makefile
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@ -8,18 +8,21 @@ ArtyA7: export XILINX_PART := xc7a100tcsg324-1
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
ArtyA7: export board := ArtyA7
ArtyA7: export SYSTEMCLOCK := 20000000
ArtyA7: export MAXSDCCLOCK := 5000000
ArtyA7: FPGA_Arty
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
vcu118: export board := vcu118
vcu118: export SYSTEMCLOCK := 71000000
ArtyA7: export MAXSDCLOCK := 1000000
vcu118: FPGA_VCU
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
vcu108: export board := vcu108
vcu108: export SYSTEMCLOCK := 50000000
ArtyA7: export MAXSDCLOCK := 12500000
vcu108: FPGA_VCU
# variables computed from config

9
fpga/zsbl/Makefile
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@ -28,15 +28,16 @@ LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf
LINKER :=linker1000.x
# FGPA parameters
SYSTEMCLOCK ?= 20000000
EXT_MEM_BASE ?= 0x80000000
EXT_MEM_RANGE ?= 0x10000000
SYSTEMCLOCK ?= 20000000
MAXSDCCLOCK ?= 5000000
EXT_MEM_BASE ?= 0x80000000
EXT_MEM_RANGE ?= 0x10000000
AFLAGS =$(MARCH) $(MABI) -W
# Override directive allows us to prepend other options on the command line
# e.g. $ make CFLAGS=-g
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${SYSTEMCLOCK} -DEXT_MEM_BASE=${EXT_MEM_BASE} -DEXT_MEM_RANGE=${EXT_MEM_RANGE}
override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${SYSTEMCLOCK} -DMAXSDCCLOCK=${MAXSDCCLOCK} -DEXT_MEM_BASE=${EXT_MEM_BASE} -DEXT_MEM_RANGE=${EXT_MEM_RANGE}
AS=riscv64-unknown-elf-as
CC=riscv64-unknown-elf-gcc
AR=riscv64-unknown-elf-ar

7
fpga/zsbl/boot.h
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@ -64,13 +64,6 @@ typedef QWORD LBA_t;
// Export disk_read
int disk_read(BYTE * buf, LBA_t sector, UINT count);
// now defined in system.h
//#define SYSTEMCLOCK 50000000
// TODO: This line needs to change back to 20MHz when we fix the
// timing problems.
#define MAXSDCCLOCK 12500000
// Maximum SDC speed is either the system clock divided by 2 (because
// of the SPI peripheral clock division) or the maximum speed an SD
// card can be pushed to.

4
fpga/zsbl/system.h
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@ -5,6 +5,10 @@
#define SYSTEMCLOCK 100000000
#endif
#ifndef MAXSDCCLOCK
#define MAXSDCCLOCK 5000000
#endif
#ifndef EXT_MEM_BASE
#define EXT_MEM_BASE 0x80000000
#endif