31 Commits

Author	SHA1	Message	Date
Jordan Carlin	410c279396	add --define support to verilator	2024-12-08 01:55:15 -08:00
Jordan Carlin	59bedb78c5	Cleanup verilator paths	2024-12-07 13:24:10 -08:00
Jordan Carlin	c776ef3fd4	enable assertions in Verilator	2024-11-10 22:20:51 -08:00
Jordan Carlin	d007f3f66f	remove deprecated verilator scripts	2024-09-30 10:44:36 -07:00
Jordan Carlin	78bd6822c6	Add --params argument to wsim and use for overriding top-level params	2024-08-11 13:08:16 -07:00
Jordan Carlin	c19916a1d0	Allow Verilator to pass extra args at compile time (like -G...)	2024-08-10 12:18:54 -07:00
Rose Thompson	7223b15134	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
Rose Thompson	9471dcd296	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.	2024-07-19 17:08:47 -05:00
Rose Thompson	46ace521c6	Updated verilator makefile.	2024-06-19 16:25:31 -05:00
David Harris	bfd3c9fe86	Fixed gettenvval when variable is undefined per verilator Issue 5179	2024-06-14 07:09:53 -07:00
David Harris	61e559606e	Fixed wsim to be able to invoke TestFloat with Verilator. However, TestFloat produces incorrect results with Verilator	2024-05-09 18:56:59 -07:00
Kunlin Han	cde284d003	Fix the problem of missing sim/verilator/wkdir	2024-04-30 10:48:42 -07:00
David Harris	8f0c68373e	Verilator fulladder example improvmeents	2024-04-28 22:08:00 -07:00
David Harris	0dc2c7d16a	Fixed deriv path in Verilator makefile	2024-04-23 10:19:08 -07:00
David Harris	f9eec8c43f	Merged wsim changes	2024-04-22 13:11:35 -07:00
Kunlin Han	9be0303493	Add support for dumping vcd.	2024-04-22 13:03:51 -07:00
David Harris	cc236bdb25	Resolved merge conflicts	2024-04-22 12:16:06 -07:00
Kunlin Han	c134b712c4	Merge branch 'main' into verilator	2024-04-22 11:35:18 -07:00
Kunlin Han	c383bef1ad	Run verilator configurations and testsuites in different folders.	2024-04-22 11:32:46 -07:00
David Harris	45196a9959	ignore VCS junk files	2024-04-21 19:49:55 -07:00
David Harris	3cb5cd0cb1	simulator cleanup	2024-04-20 14:12:55 -07:00
David Harris	c8e7a6990d	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-04-20 11:44:27 -07:00
David Harris	bf2f6859e4	Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere	2024-04-20 11:27:54 -07:00
Kunlin Han	91a88fa46c	Update sim/verilator/Makefile with more comments and merging variables.	2024-04-17 09:52:54 -07:00
Kunlin Han	392eedb342	Update sim/verilator/Makefile with constants for simplicity.	2024-04-16 18:54:11 -07:00
Kunlin Han	6f6b1fd1fd	Add extra path to search for deriv/buildroot.	2024-04-16 18:45:21 -07:00
Kunlin Han	7b5972ea82	Merge branch 'verilator_getenv' into wsim_verilator	2024-04-12 15:27:09 -07:00
Kunlin Han	4d9de94029	Add support for getenvval as wrapper for Verilator's getenv.	2024-04-12 14:59:04 -07:00
Kunlin Han	a55bb01d1d	Update README and put logs in the right places.	2024-04-11 20:16:55 -07:00
Kunlin Han	e25177cf4c	Add verilator support for wsim.	2024-04-11 20:02:20 -07:00
David Harris	a8a03d6011	Reorganizing sim directory for multiple simulators	2024-04-05 18:19:46 -07:00